| Full intermetallic joints for chip stacking by using thermal gradient bonding TL Yang, T Aoki, K Matsumoto, K Toriyama, A Horibe, H Mori, Y Orii, ... Acta Materialia 113, 90-97, 2016 | 86 | 2016 |
| IMC bonding for 3D interconnection K Sakuma, K Sueoka, S Kohara, K Matsumoto, H Noma, T Aoki, Y Oyama, ... 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC …, 2010 | 74 | 2010 |
| Thermal resistance measurements of interconnections, for the investigation of the thermal resistance of a three-dimensional (3D) chip stack K Matsumoto, Y Taira 2009 25th Annual IEEE Semiconductor Thermal Measurement and Management …, 2009 | 46 | 2009 |
| Three level stacked reflective display K Matsumoto, LT Romankiw, K Sueoka, Y Taira, K Takeda US Patent 6,844,957, 2005 | 44 | 2005 |
| Channel specific rate constants relevant to the thermal decomposition of disilane K Matsumoto, SJ Klippenstein, K Tonokura, M Koshi The Journal of Physical Chemistry A 109 (22), 4911-4920, 2005 | 38 | 2005 |
| Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack K Matsumoto, S Ibaraki, K Sueoka, K Sakuma, H Kikuchi, Y Orii, ... 2011 27th Annual IEEE Semiconductor Thermal Measurement and Management …, 2011 | 32 | 2011 |
| Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements K Matsumoto, S Ibaraki, K Sueoka, K Sakuma, H Kikuchi, Y Orii, ... 2012 28th Annual IEEE Semiconductor Thermal Measurement and Management …, 2012 | 30 | 2012 |
| Investigations of cooling solutions for three-dimensional (3D) chip stacks K Matsumoto, S Ibaraki, M Sato, K Sakuma, Y Orii, F Yamada 2010 26th Annual IEEE Semiconductor Thermal Measurement and Management …, 2010 | 29 | 2010 |
| Reaction mechanism of silicon Cat-CVD S Nakamura, K Matsumoto, A Susa, M Koshi Journal of Non-Crystalline Solids 352 (9-20), 919-924, 2006 | 27 | 2006 |
| Thermal stresses of through silicon vias and si chips in three dimensional system in package T Kinoshita, T Kawakami, T Hori, K Matsumoto, S Kohara, Y Orii, ... Journal of Electronic Packaging 134 (2), 020903, 2012 | 24 | 2012 |
| Photolysis of Disilane at 193 nm N Tada, K Tonokura, K Matsumoto, M Koshi, A Miyoshi, H Matsui The Journal of Physical Chemistry A 103 (2), 322-329, 1999 | 22 | 1999 |
| Mechanism and Product Branching Ratios of the SiH3 + SiH3 Reaction K Matsumoto, M Koshi, K Okawa, H Matsui The Journal of Physical Chemistry 100 (21), 8796-8801, 1996 | 21 | 1996 |
| Thermal design guidelines for a three-dimensional (3D) chip stack, including cooling solutions K Matsumoto, S Ibaraki, K Sueoka, K Sakuma, H Kikuchi, Y Orii, ... 29th IEEE Semiconductor Thermal Measurement and Management Symposium, 1-6, 2013 | 18 | 2013 |
| Enhanced centrifugal percolating thermal underfills based on neck formation by capillary bridging JV Goicochea, T Brunschwiler, J Zürcher, H Wolf, K Matsumoto, B Michel 13th InterSociety Conference on Thermal and Thermomechanical Phenomena in …, 2012 | 14 | 2012 |
| Substrate device and electric circuit arrangement having first substrate section perpendicular to second substrate section TJ Brunschwiler, D Gschwend, K Matsumoto, SS Oggioni, G Schlottig, ... US Patent 9,433,077, 2016 | 13 | 2016 |
| Thermal characterization of a three-dimensional (3D) chip stack K Matsumoto, Y Taira Transactions of The Japan Institute of Electronics Packaging 2 (1), 153-159, 2009 | 11 | 2009 |
| Effect of underfill properties on thermomechanical stress in fine pitch 3d-ic package A Horibe, S Kohara, K Sueoka, K Matsumoto, Y Orii, F Yamada Proceedings of ICEP-IAAC 2012, 11-16, 2012 | 10 | 2012 |
| Investigation of the thermal resistance of a three-dimensional (3D) chip stack from the thermal resistance measurement and modeling of a single-stacked-chip K Matsumoto Internatinal Conference on Electronics Packaging, 2008 478, 2008 | 9 | 2008 |
| Achieving power supply and heat dissipation (cooling) in three-dimensional multilayer package K Matsumoto US Patent 9,330,213, 2016 | 8 | 2016 |
| Advanced interconnect technologies in the era of cognitive computing Y Orii, A Horibe, K Matsumoto, T Aoki, K Sueoka, S Kohara, K Okamoto, ... 2016 Pan Pacific Microelectronics Symposium (Pan Pacific), 1-6, 2016 | 8 | 2016 |
