| A scalable algorithm for minimal unsatisfiable core extraction N Dershowitz, Z Hanna, A Nadel Theory and Applications of Satisfiability Testing-SAT 2006: 9th …, 2006 | 117 | 2006 |
| A lazy and layered SMT () solver for hard industrial verification problems R Bruttomesso, A Cimatti, A Franzén, A Griggio, Z Hanna, A Nadel, A Palti, ... International Conference on Computer Aided Verification, 547-560, 2007 | 107 | 2007 |
| Bounded model checking with QBF N Dershowitz, Z Hanna, J Katz Theory and Applications of Satisfiability Testing: 8th International …, 2005 | 104 | 2005 |
| Parallel multithreaded satisfiability solver: Design and implementation Y Feldman, N Dershowitz, Z Hanna Electronic Notes in Theoretical Computer Science 128 (3), 75-90, 2005 | 84 | 2005 |
| A signal correlation guided ATPG solver and its applications for solving difficult industrial cases F Lu, LC Wang, KT Cheng, J Moondanos, Z Hanna Proceedings of the 40th annual Design Automation Conference, 436-441, 2003 | 60 | 2003 |
| Encoding RTL constructs for MathSAT: a preliminary report M Bozzano, R Bruttomesso, A Cimatti, A Franzén, Z Hanna, ... Electronic Notes in Theoretical Computer Science 144 (2), 3-14, 2006 | 51 | 2006 |
| A proof engine approach to solving combinational design automation problems G Andersson, P Bjesse, B Cook, Z Hanna Proceedings of the 39th annual design automation conference, 725-730, 2002 | 51 | 2002 |
| A clause-based heuristic for SAT solvers N Dershowitz, Z Hanna, A Nadel International conference on theory and applications of satisfiability …, 2005 | 49 | 2005 |
| Industrial strength SAT-based alignability algorithm for hardware equivalence verification D Kaiss, M Skaba, Z Hanna, Z Khasidashvili Formal Methods in Computer Aided Design (FMCAD'07), 20-26, 2007 | 40 | 2007 |
| Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints Z Khasidashvili, M Skaba, D Kaiss, Z Hanna IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 34 | 2004 |
| CLEVER: Divide and conquer combinational logic equivalence verification with false negative elimination J Moondanos, CH Seger, Z Hanna, D Kaiss Computer Aided Verification: 13th International Conference, CAV 2001 Paris …, 2001 | 32 | 2001 |
| An efficient diagnostic test pattern generation framework using boolean satisfiability F Zheng, KT Cheng, X Yan, J Moondanos, Z Hanna 16th Asian Test Symposium (ATS 2007), 288-294, 2007 | 31 | 2007 |
| Towards a better understanding of the functionality of a conflict-driven SAT solver N Dershowitz, Z Hanna, A Nadel Theory and Applications of Satisfiability Testing–SAT 2007: 10th …, 2007 | 31 | 2007 |
| Method and system for formal verification of a circuit model using binary decision diagrams J Moondanos, CJ Seger, Z Hanna, DA Kaiss US Patent 6,564,358, 2003 | 25 | 2003 |
| Simultaneous SAT-based model checking of safety properties Z Khasidashvili, A Nadel, A Palti, Z Hanna Hardware and Software, Verification and Testing: First International Haifa …, 2006 | 21 | 2006 |
| Method and device for verification of VLSI designs A Levin, Z Hanna, C Seger US Patent 6,567,959, 2003 | 21 | 2003 |
| Eureka-2006 SAT solver A Nadel, M Gordon, A Palti, Z Hanna Solver description, SAT Race 2006, 2006 | 18 | 2006 |
| An enhanced cut-points algorithm in formal equivalence verification Z Khasidashvili, J Moondanos, D Kaiss, Z Hanna Sixth IEEE International High-Level Design Validation and Test Workshop, 171-176, 2001 | 18 | 2001 |
| SAT-based methods for sequential hardware equivalence verification without synchronization Z Khasidashvili, Z Hanna Electronic Notes in Theoretical Computer Science 89 (4), 593-607, 2003 | 17 | 2003 |
| Functional property ranking A Ben-Tzur, Z Hanna US Patent 8,739,092, 2014 | 16 | 2014 |
