| A 16nm FinFET CMOS technology for mobile SoC and computing applications SY Wu, CY Lin, MC Chiang, JJ Liaw, JY Cheng, SH Yang, M Liang, ... 2013 IEEE International Electron Devices Meeting, 9.1. 1-9.1. 4, 2013 | 193 | 2013 |
| A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications SY Wu, CY Lin, MC Chiang, JJ Liaw, JY Cheng, SH Yang, CH Tsai, ... 2016 IEEE International Electron Devices Meeting (IEDM), 2.6. 1-2.6. 4, 2016 | 157 | 2016 |
| Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM T Tanaka, E Yoshida, T Miyashita IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 155 | 2004 |
| Memory cell array, method of producing the same, and semiconductor memory device using the same E Yoshida, T Tanaka, T Miyashita US Patent 7,671,417, 2010 | 153 | 2010 |
| Manufacturing method of semiconductor device suppressing short-channel effect T Miyashita, K Suzuki US Patent 7,223,646, 2007 | 121 | 2007 |
| Manufacturing method of semiconductor device suppressing short-channel effect T Miyashita, K Suzuki US Patent 7,312,500, 2007 | 118 | 2007 |
| Semiconductor device and manufacturing method thereof T Miyashita, K Suzuki US Patent App. 11/192,424, 2006 | 101 | 2006 |
| An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance … SY Wu, CY Lin, MC Chiang, JJ Liaw, JY Cheng, SH Yang, SZ Chang, ... 2014 IEEE International Electron Devices Meeting, 3.1. 1-3.1. 4, 2014 | 84 | 2014 |
| High-performance and low-power bulk logic platform utilizing FET specific multiple-stressors with highly enhanced strain and full-porous low-k interconnects for 45-nm CMOS … T Miyashita, K Ikeda, YS Kim, T Yamamoto, Y Sambonsugi, H Ochimizu, ... 2007 IEEE International Electron Devices Meeting, 251-254, 2007 | 32 | 2007 |
| A study of highly scalable DG-FinDRAM E Yoshida, T Miyashita, T Tanaka IEEE electron device letters 26 (9), 655-657, 2005 | 31 | 2005 |
| Demonstration of a sub-0.03 um2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node SY Wu, CY Lin, MC Chiang, JJ Liaw, JY Cheng, CH Chang, VS Chang, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 28 | 2016 |
| Junction profile engineering with a novel multiple laser spike annealing scheme for 45-nm node high performance and low leakage CMOS technology T Yamamoto, T Kubo, T Sukegawa, E Takii, Y Shimamune, N Tamura, ... 2007 IEEE International Electron Devices Meeting, 143-146, 2007 | 28 | 2007 |
| Scaled, novel effective workfunction metal gate stacks for advanced low-V T, gate-all-around vertically stacked nanosheet FETs with reduced vertical distance between sheets A Veloso, E Simoen, A Oliveira, A Chasin, SC Chen, Y Lin, T Miyashita, ... International Conference on Solid State Devices and Materials, 2019 | 24 | 2019 |
| Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and its optimization for beyond 45-nm high-performance applications T Miyashita, T Owada, A Hatada, Y Hayami, K Ookoshi, T Mori, H Kurata, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 15 | 2008 |
| Experimental evaluation of depth-dependent lateral standard deviation for various ions in a-Si from one-dimensional tilted implantation profiles T Miyashita, K Suzuki IEEE Transactions on Electron Devices 46 (9), 1824-1828, 1999 | 15 | 1999 |
| Semiconductor device and method of manufacturing same T Miyashita, K Ikeda US Patent App. 12/561,841, 2010 | 13 | 2010 |
| Advantages of a new scheme of junction profile engineering with laser spike annealing and its integration into a 45-nm node high performance CMOS technology T Yamamoto, T Kubo, T Sukegawa, A Katakami, Y Shimamune, N Tamura, ... 2007 IEEE Symposium on VLSI Technology, 122-123, 2007 | 13 | 2007 |
| Highly conductive metal gate fill integration solution for extremely scaled RMG stack for 5 nm & beyond N Yoshida, S Hassan, W Tang, Y Yang, W Zhang, SC Chen, L Dong, ... 2017 IEEE International Electron Devices Meeting (IEDM), 22.2. 1-22.2. 4, 2017 | 12 | 2017 |
| 45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications M Okuno, K Okabe, T Sakuma, K Suzuki, T Miyashita, T Yao, H Morioka, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 52-55, 2005 | 12 | 2005 |
| High voltage I/O FinFET device optimization for 16nm system-on-a-chip (SoC) technology T Miyashita, KC Kwong, PH Wu, BC Hsu, PN Chen, CH Tsai, MC Chiang, ... 2015 Symposium on VLSI Technology (VLSI Technology), T152-T153, 2015 | 11 | 2015 |
