| Leakage reduction of SRAM-based look-up table using dynamic power gating A Nag, D Nath, SN Pradhan Journal of Circuits, Systems and Computers 26 (03), 1750041, 2017 | 11 | 2017 |
| An autonomous clock gating technique in finite state machines based on registers partitioning A Nag, SN Pradhan Journal of Circuits, Systems and Computers 25 (05), 1650033, 2016 | 8 | 2016 |
| Low-power FSM synthesis based on automated power and clock gating technique A Nag, S Das, SN Pradhan Journal of Circuits, Systems and Computers 28 (05), 1920003, 2019 | 6 | 2019 |
| Design of power gated SRAM cell for reducing the NBTI effect and leakage power dissipation during the hold operation A Bhattacharjee, A Nag, K Das, SN Pradhan Journal of Electronic Testing 38 (1), 91-105, 2022 | 5 | 2022 |
| CG-in-PG architecture implementation for power reduction in FSMs P Choudhury, A Nag, D Nath, SN Pradhan International Journal of Electronics Letters 2 (3), 180-185, 2014 | 3 | 2014 |
| Power gating architecture implementation inside clock period to reduce power D Nath, P Choudhury, A Nag, SN Pradhan International Journal of Computer Aided Engineering and Technology 5 6 (3 …, 2014 | 3 | 2014 |
| Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA VK Singh, A Nag, A Bhattacharjee, SN Pradhan Journal of Circuits, Systems and Computers 32 (07), 2350113, 2023 | 2 | 2023 |
| A novel NOR gate-based dynamic power gating technique in SRAM A Nag, K Ruchira Reddy, N Majumder, E Debbarma, SN Pradhan Proceedings of the Fourth International Conference on Microelectronics …, 2021 | 2 | 2021 |
| Low power transistor level synthesis of finite state machines using a novel dual gating technique A Nag, S Das, SN Pradhan International Journal of Embedded Systems 13 (4), 431-438, 2020 | 2 | 2020 |
| An Autonomous Power and Clock Gating Technique in SRAM-Based FPGA A Nag, SN Pradhan Proceedings of the International Conference on Nano-electronics, Circuits …, 2017 | 2 | 2017 |
| Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks VK Singh, A Nag, SN Pradhan International Journal of Embedded Systems 15 (4), 326-332, 2022 | 1 | 2022 |
| Within-clock power gating architecture implimentation to reduce leakage SN Pradhan, D Nath, P Choudhury, A Nag 2012 5th International Conference on Computers and Devices for Communication …, 2012 | 1 | 2012 |
| Low power design of 16-bit synchronous counter by introducing effective clock monitoring circuits VK Singh, A Nag, A Das, SN Pradhan Songklanakarin Journal of Science and Technology, 2023 | | 2023 |
| A CLB Priority based Power Gating Technique in Field Programmable Gate Arrays A Nag, SN Pradhan International Journal of Image, Graphics and Signal Processing 11 (5), 15, 2018 | | 2018 |
| Design of new high-speed and low-energy dynamic PLA SN Pradhan, S Bhowmik, P Choudhury, D Nath, A Nag, D Deb, B Paul International Journal of Electronics Letters 4 (1), 87-92, 2016 | | 2016 |
| Layout-oriented look up table-based dual threshold approach to reduce leakage SN Pradhan, A Chakraborty, A Nag, D Nath International Journal of Computer Aided Engineering and Technology 7 (4 …, 2015 | | 2015 |
