| Energy-and performance-aware mapping for regular NoC architectures J Hu, R Marculescu IEEE Transactions on computer-aided design of integrated circuits and …, 2005 | 892 | 2005 |
| Energy-aware mapping for tile-based NoC architectures under performance constraints J Hu, R Marculescu Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003 | 801 | 2003 |
| DyAD: smart routing for networks-on-chip J Hu, R Marculescu Proceedings of the 41st annual Design Automation Conference, 260-263, 2004 | 742 | 2004 |
| Key research problems in NoC design: a holistic perspective UY Ogras, J Hu, R Marculescu Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware …, 2005 | 494 | 2005 |
| Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures J Hu, R Marculescu 2003 Design, Automation and Test in Europe Conference and Exhibition, 688-693, 2003 | 384 | 2003 |
| Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints J Hu, R Marculescu Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 355 | 2004 |
| System-level buffer allocation for application-specific networks-on-chip router design J Hu, UY Ogras, R Marculescu IEEE Transactions on Computer-Aided Design of integrated circuits and …, 2006 | 255 | 2006 |
| Application-specific buffer space allocation for networks-on-chip router design J Hu, R Marculescu IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 240 | 2004 |
| Architecting voltage islands in core-based system-on-a-chip designs J Hu, Y Shin, N Dhanwada, R Marculescu Proceedings of the 2004 international symposium on Low power electronics and …, 2004 | 177 | 2004 |
| Communication and task scheduling of application-specific networks-on-chip J Hu, R Marculescu IEE Proceedings-Computers and Digital Techniques 152 (5), 643-651, 2005 | 109 | 2005 |
| System-level point-to-point communication synthesis using floorplanning information [soc] J Hu, Y Deng, R Marculescu Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002 | 82 | 2002 |
| Energy and reliability oriented mapping for regular networks-on-chip C Ababei, HS Kia, OP Yadav, J Hu Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on …, 2011 | 42 | 2011 |
| System and method for reducing reconfiguration power RR Huang, M Voogel, J Hu, S Teig US Patent 8,912,820, 2014 | 35 | 2014 |
| Design methodologies for application specific networks-on-chip J Hu Carnegie Mellon University, 2005 | 28 | 2005 |
| Ocin tsim-DVFS aware simulator for NoCs S Prabhu, B Grot, P Gratz, J Hu Proc. SAW 1, 2010 | 26 | 2010 |
| Method of physical planning voltage islands for ASICs and system-on-chip designs NR Dhanwada, Y Shin, J Hu US Patent 7,296,251, 2007 | 25 | 2007 |
| Communication-centric SoC design for nanoscale domain UY Ogras, J Hu, R Marculescu 2005 IEEE International Conference on Application-Specific Systems …, 2005 | 24 | 2005 |
| System and method for reducing reconfiguration power usage RR Huang, M Voogel, J Hu, S Teig US Patent 8,806,404, 2014 | 17 | 2014 |
| System and method for reducing reconfiguration power usage RR Huang, M Voogel, J Hu, S Teig US Patent 9,143,128, 2015 | 12 | 2015 |
| System and method for reducing reconfiguration power usage RR Huang, M Voogel, J Hu, S Teig US Patent 9,362,909, 2016 | 3 | 2016 |
