| A 40 mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting JP Im, SW Wang, ST Ryu, GH Cho IEEE Journal of Solid-State Circuits 47 (12), 3055-3067, 2012 | 294 | 2012 |
| Fully flexible, lightweight, high performance all-solid-state supercapacitor based on 3-Dimensional-graphene/graphite-paper A Ramadoss, KY Yoon, MJ Kwak, SI Kim, ST Ryu, JH Jang Journal of Power Sources 337, 159-165, 2017 | 275 | 2017 |
| A decision-error-tolerant 45 nm CMOS 7b 1 GS/s nonbinary 2b/cycle SAR ADC HK Hong, W Kim, HW Kang, SJ Park, M Choi, HJ Park, ST Ryu IEEE Journal of Solid-State Circuits 50 (2), 543-555, 2014 | 172* | 2014 |
| A 550-uW 10-b 40-MS/s SAR ADC with Multistep Addition-only Digital Error Correction SH Cho, CK Lee, JK Kwon, ST Ryu Solid-State Circuits, IEEE Journal of 46 (8), 1881-1892, 2011 | 156* | 2011 |
| A 10-bit 50-MS/s pipelined ADC with opamp current reuse ST Ryu, BS Song, K Bacrania IEEE Journal of Solid-State Circuits 42 (3), 475-485, 2007 | 147 | 2007 |
| Realization of high performance flexible wire supercapacitors based on 3-dimensional NiCo 2 O 4/Ni fibers A Ramadoss, KN Kang, HJ Ahn, SI Kim, ST Ryu, JH Jang Journal of materials chemistry A 4 (13), 4718-4727, 2016 | 109 | 2016 |
| A 14-b linear capacitor self-trimming pipelined ADC ST Ryu, S Ray, BS Song, GH Cho, K Bacrania IEEE Journal of Solid-State Circuits 39 (11), 2046-2051, 2004 | 101 | 2004 |
| A 0.6 V 12 b 10 MS/s low-noise asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC W Kim, HK Hong, YJ Roh, HW Kang, SI Hwang, DS Jo, DJ Chang, ... IEEE Journal of Solid-State Circuits 51 (8), 1826-1839, 2016 | 92 | 2016 |
| Digital feedforward sigma-delta modulator in analog-to-digital converter and modulation method thereof YS Jang, SG Lee, ST Ryu US Patent 8,120,518, 2012 | 91 | 2012 |
| A 6-b 4.1-GS/s flash ADC with time-domain latch interpolation in 90-nm CMOS JI Kim, W Kim, ST Ryu IEEE Journal of Solid-State Circuits 48 (6), 1429-1441, 2013 | 84* | 2013 |
| A 10-bit column-driver IC with parasitic-insensitive iterative charge-sharing based capacitor-string interpolation for mobile active-matrix LCDs HS Kim, JH Yang, SH Park, ST Ryu, GH Cho IEEE Journal of Solid-State Circuits 49 (3), 766-782, 2014 | 78* | 2014 |
| A highly noise-immune touch controller using filtered-delta-integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels JH Yang, SH Park, JM Choi, HS Kim, CB Park, ST Ryu, GH Cho 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 75 | 2013 |
| 26.4 A 21fJ/conv-step 9 ENOB 1.6 GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS DS Jo, IH Jang, DS Lee, YS You, YH Lee, HJ Park, ST Ryu 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 71 | 2015 |
| A 2.6 b/cycle-architecture-based 10b 1.7 GS/s 15.4 mW 4x-time-Interleaved SAR ADC with a multistep hardware-retirement technique HK Hong, HW Kang, DS Jo, DS Lee, YS You, YH Lee, HJ Park, ST Ryu 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 71 | 2015 |
| A long reset-time power-on reset circuit with brown-out detection capability HB Le, XD Do, SG Lee, ST Ryu IEEE Transactions on Circuits and Systems II: Express Briefs 58 (11), 778-782, 2011 | 69 | 2011 |
| A delta-readout scheme for low-power CMOS image sensors with multi-column-parallel SAR ADCs HJ Kim, SI Hwang, JW Kwon, DH Jin, BS Choi, SG Lee, JH Park, JK Shin, ... IEEE Journal of Solid-State Circuits 51 (10), 2262-2273, 2016 | 67* | 2016 |
| An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement HK Hong, HW Kang, B Sung, CH Lee, M Choi, HJ Park, ST Ryu 2013 IEEE international solid-state circuits conference digest of technical …, 2013 | 67 | 2013 |
| A noise-immune high-speed readout circuit for in-cell touch screen panels JH Yang, SC Jung, YS Son, ST Ryu, GH Cho IEEE Transactions on Circuits and Systems I: Regular Papers 60 (7), 1800-1809, 2013 | 65* | 2013 |
| A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration DR Oh, JI Kim, DS Jo, WC Kim, DJ Chang, ST Ryu IEEE Journal of Solid-State Circuits 54 (1), 288-297, 2018 | 64* | 2018 |
| A precise decibel-linear programmable gain amplifier using a constant current-density function SY Kang, ST Ryu, CS Park IEEE Transactions on Microwave Theory and Techniques 60 (9), 2843-2850, 2012 | 59 | 2012 |
Gyu-Hyeong ChoProfessor of Electrical Engineering, KAIST在 kaist.ac.kr 的电子邮件经过验证
