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Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene J Kim, C Bayram, H Park, CW Cheng, C Dimitrakopoulos, JA Ott, ... Nature communications 5 (1), 4836, 2014 | 408 | 2014 |
Characteristics and device design of sub-100 nm strained Si N-and PMOSFETs K Rim, J Chu, H Chen, KA Jenkins, T Kanarsky, K Lee, A Mocuta, H Zhu, ... 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2002 | 371 | 2002 |
Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs) AW Topol, DC La Tulipe, L Shi, SM Alam, DJ Frank, SE Steen, J Vichiconti, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 352 | 2005 |
Strained Si NMOSFETs for high performance CMOS technology K Rim, S Koester, M Hargrove, J Chu, PM Mooney, J Ott, T Kanarsky, ... 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2001 | 346 | 2001 |
Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs K Rim, K Chan, L Shi, D Boyd, J Ott, N Klymko, F Cardone, L Tai, ... IEEE International Electron Devices Meeting 2003, 3.1. 1-3.1. 4, 2003 | 293 | 2003 |
Sharp reduction of contact resistivities by effective Schottky barrier lowering with silicides as diffusion sources Z Zhang, F Pagette, C D'emic, B Yang, C Lavoie, Y Zhu, M Hopstaken, ... IEEE Electron Device Letters 31 (7), 731-733, 2010 | 290 | 2010 |
High speed composite p-channel Si/SiGe heterostructure for field effect devices JO Chu, R Hammond, KEE Ismail, SJ Koester, PM Mooney, JA Ott US Patent 6,350,993, 2002 | 272 | 2002 |
High performance strained silicon FinFETs device and method for forming same SW Bedell, KK Chan, D Chidambarrao, SH Christianson, JO Chu, ... US Patent 7,705,345, 2010 | 249 | 2010 |
High-/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length MH Khater, Z Zhang, J Cai, C Lavoie, C D'Emic, Q Yang, B Yang, ... IEEE Electron Device Letters 31 (4), 275-277, 2010 | 245 | 2010 |
Hybrid-orientation technology (HOT): Opportunities and challenges M Yang, VWC Chan, KK Chan, L Shi, DM Fried, JH Stathis, AI Chou, ... IEEE Transactions on Electron Devices 53 (5), 965-978, 2006 | 222 | 2006 |
Kerf-less removal of Si, Ge, and III–V layers by controlled spalling to enable low-cost PV technologies SW Bedell, D Shahrjerdi, B Hekmatshoar, K Fogel, PA Lauro, JA Ott, ... IEEE Journal of Photovoltaics 2 (2), 141-147, 2012 | 214 | 2012 |
Electrical characterization of germanium p-channel MOSFETs H Shang, H Okorn-Schimdt, J Ott, P Kozlowski, S Steen, EC Jones, ... IEEE Electron Device Letters 24 (4), 242-244, 2003 | 208 | 2003 |
Bulk and strained silicon on insulator using local selective oxidation JO Chu, KEE Ismail, KY Lee, JA Ott US Patent 5,963,817, 1999 | 186 | 1999 |
Bulk and strained silicon on insulator using local selective oxidation JO Chu, KEE Ismail, KY Lee, JA Ott US Patent 6,251,751, 2001 | 179 | 2001 |
Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers J de Souza, J Ott, A Reznicek, K Saenger US Patent App. 10/725,850, 2005 | 176 | 2005 |
Hafnium oxide gate dielectrics on sulfur-passivated germanium MM Frank, SJ Koester, M Copel, JA Ott, VK Paruchuri, H Shang, ... Applied physics letters 89 (11), 2006 | 175 | 2006 |
High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric H Shang, H Okorn-Schmidt, KK Chan, M Copel, JA Ott, PM Kozlowski, ... Digest. International Electron Devices Meeting,, 441-444, 2002 | 162 | 2002 |
High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes SJ Han, J Tang, B Kumar, A Falk, D Farmer, G Tulevski, K Jenkins, ... Nature nanotechnology 12 (9), 861-865, 2017 | 154 | 2017 |
Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique DF Canaperi, JO Chu, PD Christopher, L Huang, JA Ott, HSP Wong US Patent 6,524,935, 2003 | 150 | 2003 |