| A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications A Mukherjee, P Debnath, D Nirmal, M Chanda Microelectronics Journal 133, 105689, 2023 | 5 | 2023 |
| Analysis of double-gate junctionless MOSFET for energy efficient digital application A Mukherjee, D Banerjee, T Ganguli, A Sarkar 2021 Devices for Integrated Circuit (DevIC), 545-549, 2021 | 4 | 2021 |
| Advantages of charge plasma based double gate Junctionless MOSFET over bulk MOSFET for label free Biosensing A Bhattacharyya, A Mukherjee, M Chanda, D De 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 99-104, 2020 | 4 | 2020 |
| Analytical Modeling of Core–Shell Junctionless RADFET dosimeter of Improved Sensitivity S Ghosh, P Saha, A Mukherjee, S Bose, P Venkateswaran, SK Sarkar Silicon 14 (14), 9091-9102, 2022 | 3 | 2022 |
| Impact of Temperature on Circuit Performances of Junctionless MOSFET in Sub-threshold Regime A Mukherjee, B Ray, D Das, S Bhattacharyya, P Debnath, M Chanda 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 1-5, 2020 | 2 | 2020 |
| Machine learning-based output prediction of negative capacitance tunnel-FET A Mukherjee, P Debnath, M Chanda International Journal of Electronics 111 (8), 1331-1345, 2024 | | 2024 |
| A junctionless dual-gate MOSFET-based programmable inverter for secured hardware applications using nitride charge trapping A Karmakar, A Mukherjee, S Dhar, D Sen, M Chanda Semiconductor Science and Technology 37 (11), 115013, 2022 | | 2022 |
Manash Chanda, Ph. D (Engg.)Associate Professor and Head, Dept. of ECE, Meghnad Saha Institute of Technology, Kolkata 700150在 ieee.org 的电子邮件经过验证
