| Design methodologies based on hardware description languages T Riesgo, Y Torroja, E De la Torre IEEE Transactions on Industrial electronics 46 (1), 3-12, 1999 | 132 | 1999 |
| VHDL: Lenguaje Estándar de diseño electrónico E Villar McGraw-Hill, 1998 | 78 | 1998 |
| Power balance of a hybrid power source in a power plant for a small propulsion aircraft E Bataller-Planes, N Lapena-Rey, J Mosquera, F Ortí, JÁ Oliver, Ó GarcÍa, ... IEEE Transactions on Power Electronics 24 (12), 2856-2866, 2009 | 60 | 2009 |
| A serial port based debugging tool to improve learning with arduino Y Torroja, A López, J Portilla, T Riesgo 2015 Conference on Design of Circuits and Integrated Systems (DCIS), 1-4, 2015 | 26 | 2015 |
| Nonintrusive debugging using the JTAG interface of FPGA-based prototypes E De la Torre, M Garcia, T Riesgo, Y Torroja, J Uceda Industrial Electronics, 2002. ISIE 2002. Proceedings of the 2002 IEEE …, 2002 | 19 | 2002 |
| Design for reusability: Generic and configurable designs Y Torroja, T Riesgo, E de la Torre, J Uceda Proceedings of System Modeling and Code Reusability, 11-21, 1997 | 19 | 1997 |
| A modular environment for learning digital control applications Y Torroja, R Velasco, E Angulo, T Riesgo, E De La Torre Microelectronics Education, Marcombo, SA, 185-188, 2002 | 13 | 2002 |
| ARDID: A Tool for the Quality Analysis of VHDL based Designs Y Torroja, C Lopez, M Garcia, T Riesgo, E de la Torre, J Uceda Second International Forum on Design Languages, 1999 | 13 | 1999 |
| Teaching embedded systems and microcontrollers using scale models Y Torroja, O Garcia, T Riesgo, E De La Torre 31st Annual Conference of IEEE Industrial Electronics Society, 2005. IECON …, 2005 | 11 | 2005 |
| Disjoint region partitioning for probabilistic switching activity estimation at register transfer level F Machado, T Riesgo, Y Torroja Integrated Circuit and System Design. Power and Timing Modeling …, 2009 | 9 | 2009 |
| A method to perform error simulation in VHDL C López, T Riesgo, Y Torroja, E De La Torre, J Uceda Design of Circuits and Integrated Systems Conference, 495-500, 1998 | 9 | 1998 |
| Using a simplified hardware model to analyse the Quality of VHDL based designs Y Torroja, F Casado, F Machado, T Riesgo, E De La Torre, J Uceda User Forum at DATE, Paris (France), 2000 | 8 | 2000 |
| An artificial vision system used for the measurement of the overhead wire in railway applications Y Torroja, S Garcia, JL Aparicio, PM Martínez Proceedings of IECON'93-19th Annual Conference of IEEE Industrial …, 1993 | 8 | 1993 |
| Creativity and innovation skills in university stem education: The chet project approach C García-Aranda, A Molina-García, MC Morillo Balsera, ... 6th International Conference on Higher Education Advances (HEAd'20), 679-687, 2020 | 7 | 2020 |
| Design of a CAN interface for custom circuits J De Lucas, M Quintana, T Riesgo, Y Torroja, J Uceda IECON'99. Conference Proceedings. 25th Annual Conference of the IEEE …, 1999 | 7 | 1999 |
| Quality estimation of test vectors and functional validation procedures based on fault and error models T Riesgo, Y Torroja, E de la Torre, J Uceda Proceedings Design, Automation and Test in Europe, 955-956, 1998 | 7 | 1998 |
| A Simple Method to Estimate the Area of VHDL RTL descriptions F Machado, Y Torroja, F Casado, T Riesgo, E de la Torre, J Uceda Proceedings of the XV Design of Circuits and Integrated Systems Conference …, 2000 | 6 | 2000 |
| Custom hardware IEEE 1451.2 implementation for smart transducers A De Castro, T Riesgo, E De la Torre, Y Torroja, J Uceda IEEE 2002 28th Annual Conference of the Industrial Electronics Society …, 2002 | 5 | 2002 |
| Estimation of the quality of design validation experiments based on error models T Riesgo, Y Torroja, C López, J Uceda Proc. of VHDL Users’ Forum in Europe, 1997 | 5 | 1997 |
| VHDL L Terés, Y Torroja, S Olcoz, E Villar Lenguaje Estándar de diseño electrónico, 1997 | 5 | 1997 |
