| 16.8 A 25.4-to-29.5 GHz 10.2 mW isolated sub-sampling PLL achieving-252.9 dB jitter-power FoM and-63dBc reference spur Z Yang, Y Chen, S Yang, PI Mak, RP Martins 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 270-272, 2019 | 90 | 2019 |
| A 0.096-mm –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration H Yu, Y Chen, CC Boon, PI Mak, RP Martins IEEE Transactions on Microwave Theory and Techniques 68 (1), 144-159, 2019 | 88 | 2019 |
| A 0.044-mm2 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB H Yu, Y Chen, CC Boon, C Li, PI Mak, RP Martins IEEE Transactions on Circuits and Systems II: Express Briefs 66 (1), 71-75, 2018 | 82 | 2018 |
| A 0.083-mm2 25.2-to-29.5 GHz Multi-LC-Tank Class-F234 VCO With a 189.6-dBc/Hz FOM H Guo, Y Chen, PI Mak, RP Martins IEEE Solid-State Circuits Letters 1 (4), 86-89, 2018 | 76 | 2018 |
| 26.2 A 0.08 mm2 25.5-to-29.9 GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6 dBc/Hz FoM and 130kHz 1/f3 PN Corner H Guo, Y Chen, PI Mak, RP Martins 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 410-412, 2019 | 72 | 2019 |
| 20.1 A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f3 PN Corner Without Harmonic Tuning H Guo, Y Chen, PI Mak, RP Martins 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 294-296, 2021 | 47 | 2021 |
| A 3.3-mW 25.2-to-29.4-GHz current-reuse VCO using a single-turn multi-tap inductor and differential-only switched-capacitor arrays with a 187.6-dBc/Hz FOM Y Huang, Y Chen, H Guo, PI Mak, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3704-3717, 2020 | 46 | 2020 |
| An Area-Efficient and Tunable Bandwidth-Extension Technique for a Wideband CMOS Amplifier Handling 50+ Gb/s Signaling Y Chen, PI Mak, H Yu, CC Boon, RP Martins IEEE Transactions on Microwave Theory and Techniques 65 (12), 4960-4975, 2017 | 37 | 2017 |
| A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Y Chen, PI Mak, CC Boon, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers 65 (9), 3014-3026, 2018 | 36 | 2018 |
| High-performance harmonic-rich single-core VCO with multi-LC tank: A tutorial Y Chen, PI Mak, RP Martins IEEE Transactions on Circuits and Systems II: Express Briefs 69 (7), 3115-3121, 2022 | 33 | 2022 |
| A wideband inductorless dB-linear automatic gain control amplifier using a single-branch negative exponential generator for wireline applications L Kong, Y Chen, CC Boon, PI Mak, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers 65 (10), 3196-3206, 2018 | 31 | 2018 |
| A 50-Gb/s PAM-4 silicon-photonic transmitter incorporating lumped-segment MZM, distributed CMOS driver, and integrated CDR Q Liao, Y Zhang, S Ma, L Wang, L Li, G Li, Z Zhang, J Liu, N Wu, L Liu, ... IEEE Journal of Solid-State Circuits 57 (3), 767-780, 2021 | 28 | 2021 |
| A highly-scalable analog equalizer using a tunable and current-reusable for 10-Gb/s I/O links Y Chen, PI Mak, Y Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (5), 978-982, 2014 | 27 | 2014 |
| A 120–150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm Psat for Sub-THz Imaging System J Zhang, T Wu, L Nie, S Ma, Y Chen, J Ren IEEE Access 9, 74752-74762, 2021 | 26 | 2021 |
| Comparator with built-in reference voltage generation and split-ROM encoder for a high-speed flash ADC Y Chen, PI Mak, J Yang, R Yue, Y Wang 2015 International Symposium on Signals, Circuits and Systems (ISSCS), 1-4, 2015 | 25 | 2015 |
| A 13-bit ENOB third-order noise-shaping SAR ADC employing hybrid error control structure and LMS-based foreground digital calibration Q Zhang, N Ning, Z Zhang, J Li, K Wu, Y Chen, Q Yu IEEE Journal of Solid-State Circuits 57 (7), 2181-2195, 2022 | 24 | 2022 |
| A 0.14-to-0.29-pJ/bit 14-GBaud/s trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit in 28-nm CMOS X Zhao, Y Chen, PI Mak, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers 68 (1), 89-102, 2020 | 23 | 2020 |
| A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed … X Zhao, Y Chen, PI Mak, RP Martins 2020 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2020 | 23 | 2020 |
| A 0.002-mm6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver With 59.6% Horizontal Eye Opening Under 23.3-dB Channel Loss at Nyquist Frequency Y Chen, PI Mak, L Zhang, Y Wang IEEE Transactions on Microwave Theory and Techniques 62 (12), 3107-3117, 2014 | 23 | 2014 |
| A 10.6-mW 26.4-GHz dual-loop type-II phase-locked loop using dynamic frequency detector and phase detector Z Yang, Y Chen, S Yang, PI Mak, RP Martins IEEE Access 8, 2222-2232, 2019 | 22 | 2019 |
Pui-In Mak (Elvis)Professor at University of Macau | IEEE Fellow | IET Fellow | RSC Fellow | CAS Overseas Expert在 umac.mo 的电子邮件经过验证
