| 14.3 A 65nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy … J Yue, Z Yuan, X Feng, Y He, Z Zhang, X Si, R Liu, MF Chang, X Li, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2020 | 130 | 2020 |
| 15.2 A 2.75-to-75.9 TOPS/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and ping-pong CIM with simultaneous computation and weight updating J Yue, X Feng, Y He, Y Huang, Y Wang, Z Yuan, M Zhan, J Liu, JW Su, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 238-240, 2021 | 120 | 2021 |
| Sticker: A 0.41-62.1 TOPS/W 8Bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers Z Yuan, J Yue, H Yang, Z Wang, J Li, Y Yang, Q Guo, X Li, MF Chang, ... 2018 IEEE symposium on VLSI circuits, 33-34, 2018 | 117 | 2018 |
| 4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination … Y Liu, Z Wang, A Lee, F Su, CP Lo, Z Yuan, CC Lin, Q Wei, Y Wang, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 84-86, 2016 | 114 | 2016 |
| STICKER: An energy-efficient multi-sparsity compatible accelerator for convolutional neural networks in 65-nm CMOS Z Yuan, Y Liu, J Yue, Y Yang, J Wang, X Feng, J Zhao, X Li, H Yang IEEE Journal of Solid-State Circuits 55 (2), 465-477, 2019 | 73 | 2019 |
| A ReRAM-based nonvolatile flip-flop with self-write-termination scheme for frequent-off fast-wake-up nonvolatile processors A Lee, CP Lo, CC Lin, WH Chen, KH Hsu, Z Wang, F Su, Z Yuan, Q Wei, ... IEEE Journal of Solid-State Circuits 52 (8), 2194-2207, 2017 | 54 | 2017 |
| 7.5 A 65nm 0.39-to-140.3 TOPS/W 1-to-12b unified neural network processor using block-circulant-enabled transpose-domain acceleration with 8.1× higher TOPS/mm 2 and 6T HBST … J Yue, R Liu, W Sun, Z Yuan, Z Wang, YN Tu, YJ Chen, A Ren, Y Wang, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 138-140, 2019 | 47 | 2019 |
| 14.2 A 65nm 24.7 µJ/Frame 12.3 mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width … Z Yuan, Y Yang, J Yue, R Liu, X Feng, Z Lin, X Wu, X Li, H Yang, Y Liu 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 232-234, 2020 | 34 | 2020 |
| STICKER-IM: A 65 nm computing-in-memory NN processor using block-wise sparsity optimization and inter/intra-macro data reuse J Yue, Y Liu, Z Yuan, X Feng, Y He, W Sun, Z Zhang, X Si, R Liu, Z Wang, ... IEEE Journal of Solid-State Circuits 57 (8), 2560-2573, 2022 | 26 | 2022 |
| A 3.77 TOPS/W convolutional neural network processor with priority-driven kernel optimization J Yue, Y Liu, Z Yuan, Z Wang, Q Guo, J Li, C Yang, H Yang IEEE Transactions on Circuits and Systems II: Express Briefs 66 (2), 277-281, 2018 | 25 | 2018 |
| High pe utilization CNN accelerator with channel fusion supporting pattern-compressed sparse neural networks J Wang, S Yu, J Yue, Z Yuan, Z Yuan, H Yang, X Li, Y Liu 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 16 | 2020 |
| An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators J Wang, Z Yuan, R Liu, H Yang, Y Liu Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 16 | 2019 |
| A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving $> 4\times $ Faster Clock Frequency and $> 6\times $ Higher … Z Wang, Y Liu, A Lee, F Su, CP Lo, Z Yuan, J Li, CC Lin, WH Chen, ... IEEE Journal of Solid-State Circuits 52 (10), 2769-2785, 2017 | 16 | 2017 |
| PATH: Performance-aware task scheduling for energy-harvesting nonvolatile processors J Li, Y Liu, H Li, Z Yuan, C Fu, J Yue, X Feng, CJ Xue, J Hu, H Yang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018 | 14 | 2018 |
| CORAL: coarse-grained reconfigurable architecture for convolutional neural networks Z Yuan, Y Liu, J Yue, J Li, H Yang 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 14 | 2017 |
| Maximum energy efficiency tracking circuits for converter-less energy harvesting sensor nodes Y Sun, Z Yuan, Y Liu, X Li, Y Wang, Q Wei, Y Wang, V Narayanan, ... IEEE Transactions on Circuits and Systems II: Express Briefs 64 (6), 670-674, 2017 | 14 | 2017 |
| A sparse-adaptive CNN processor with area/performance balanced N-way set-associate PE arrays assisted by a collision-aware scheduler Z Yuan, J Wang, Y Yang, J Yue, Z Wang, X Feng, Y Wang, X Li, H Yang, ... 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 61-64, 2019 | 13 | 2019 |
| AERIS: Area/Energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip J Yue, Y Liu, F Su, S Li, Z Yuan, Z Wang, W Sun, X Li, H Yang Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 9 | 2019 |
| Cp-fpga: Energy-efficient nonvolatile fpga with offline/online checkpointing optimization Z Yuan, Y Liu, J Li, J Hu, CJ Xue, H Yang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (7 …, 2017 | 8 | 2017 |
| PACA: A pattern pruning algorithm and channel-fused high PE utilization accelerator for CNNs J Wang, S Yu, Z Yuan, J Yue, Z Yuan, R Liu, Y Wang, H Yang, X Li, Y Liu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 7 | 2022 |
