| A 2.4-GHz 20–40-MHz channel WLAN digital outphasing transmitter utilizing a delay-based wideband phase modulator in 32-nm CMOS A Ravi, P Madoglio, H Xu, K Chandrashekar, M Verhelst, S Pellerano, ... IEEE Journal of Solid-State Circuits 47 (12), 3184-3196, 2012 | 108 | 2012 |
| Digital delay-locked loop with drift sensor S Pellerano, P Madoglio US Patent 8,598,930, 2013 | 75 | 2013 |
| Time-to-digital converter for frequency synthesis based on a digital bang-bang DLL M Zanuso, P Madoglio, S Levantino, C Samori, AL Lacaita IEEE Transactions on Circuits and Systems I: Regular Papers 57 (3), 548-555, 2009 | 71 | 2009 |
| A 4.75-GHz fractional frequency divider-by-1.25 with TDC-based all-digital spur calibration in 45-nm CMOS S Pellerano, P Madoglio, Y Palaskas IEEE Journal of Solid-State Circuits 44 (12), 3422-3433, 2009 | 63 | 2009 |
| A 20dBm 2.4 GHz digital outphasing transmitter for WLAN application in 32nm CMOS P Madoglio, A Ravi, H Xu, K Chandrashekar, M Verhelst, S Pellerano, ... 2012 IEEE International Solid-State Circuits Conference, 168-170, 2012 | 61 | 2012 |
| 13.6 A 2.4 GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications P Madoglio, H Xu, K Chandrashekar, L Cuellar, M Faisal, WY Li, HS Kim, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 226-227, 2017 | 57 | 2017 |
| Quantization effects in all-digital phase-locked loops P Madoglio, M Zanuso, S Levantino, C Samori, AL Lacaita IEEE Transactions on Circuits and Systems II: Express Briefs 54 (12), 1120-1124, 2007 | 54 | 2007 |
| Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter A Ravi, O Degani, HS Kim, H Lakdawala, YW Li, P Madoglio US Patent 8,390,349, 2013 | 37 | 2013 |
| A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management K Chandrashekar, S Pellerano, P Madoglio, A Ravi, Y Palaskas 2012 IEEE International Solid-State Circuits Conference, 352-354, 2012 | 24 | 2012 |
| Segmented digital-to-time converter calibration G Palaskas, P Madoglio, S Pellerano, A Ravi, K Chandrashekar US Patent 9,209,958, 2015 | 22 | 2015 |
| A digital fractional-N PLL with a PVT and mismatch insensitive TDC utilizing equivalent time sampling technique HS Kim, C Ornelas, K Chandrashekar, D Shi, P Su, P Madoglio, WY Li, ... IEEE journal of solid-state circuits 48 (7), 1721-1729, 2013 | 22 | 2013 |
| A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ modulator based on standard cell design with time-interleaving P Madoglio, A Ravi, L Cuellar, S Pellerano, P Seddighrad, I Lomeli, ... IEEE Journal of Solid-State Circuits 45 (7), 1410-1420, 2010 | 22 | 2010 |
| A 2.5 GHz delay-based wideband OFDM outphasing modulator in 45nm-LP CMOS A Ravi, P Madoglio, M Verhelst, M Sajadieh, M Aguirre, H Xu, S Pellerano, ... 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 26-27, 2011 | 20 | 2011 |
| System, method and apparatus for an open loop calibrated phase wrapping phase modulator for wideband RF outphasing/polar transmitters A Ravi, P Madoglio, M Verhelst, G Palaskas US Patent 8,222,966, 2012 | 17 | 2012 |
| Digital phase lock loop A Ravi, PE Su, P Madoglio, G Palaskas US Patent 8,207,770, 2012 | 15 | 2012 |
| Dynamic element matching for time-to-digital converters S Pellerano, P Madoglio, A Ravi US Patent 8,198,929, 2012 | 14 | 2012 |
| A cellular multiband DTC-based digital polar transmitter with− 153 dBc/Hz noise in 14-nm FinFET Y Palaskas, P Madoglio, J Angel, J Tomasik, S Hampel, P Schubert, ... ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019 | 12 | 2019 |
| A cellular multiband DTC-based digital polar transmitter with− 153-dBc/Hz noise in 14-nm FinFET P Madoglio, Y Palaskas, J Angel, J Tomasik, S Hampel, P Schubert, ... IEEE Journal of Solid-State Circuits 55 (7), 1830-1841, 2020 | 11 | 2020 |
| Parallel digital-to-time converter architecture P Madoglio, S Pellerano US Patent 9,054,925, 2015 | 9 | 2015 |
| Delay element array for time-to-digital converters P Madoglio, S Pellerano US Patent 7,782,104, 2010 | 9 | 2010 |
