| A logic synthesis methodology for low-power ternary logic circuits S Kim, SY Lee, S Park, KR Kim, S Kang IEEE Transactions on Circuits and Systems I: Regular Papers 67 (9), 3138-3151, 2020 | 114 | 2020 |
| Ternary logic synthesis with modified Quine-McCluskey algorithm SY Lee, S Kim, S Kang 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 158-163, 2019 | 19 | 2019 |
| Design of quad-edge-triggered sequential logic circuits for ternary logic S Kim, SY Lee, S Park, S Kang 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 37-42, 2019 | 13 | 2019 |
| Construction of Realistic Place-and-route Benchmarks for Machine Learning Applications D Kim, SY Lee, K Min, S Kang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022 | 11 | 2022 |
| Compact topology-aware bus routing for design regularity D Kim, S Do, SY Lee, S Kang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 9 | 2019 |
| Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator D Kim, H Kwon, SY Lee, S Kim, M Woo, S Kang 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 6 | 2021 |
| ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks K Min, S Kwon, SY Lee, D Kim, S Park, S Kang 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, 2023 | 3 | 2023 |
| Signal-Integrity-Aware Interposer Bus Routing in 2.5 D Heterogeneous Integration SY Lee, D Kim, K Min, S Kang 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 178-183, 2022 | 3 | 2022 |
| RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization SY Lee, S Park, D Kim, M Kim, TP Le, S Kang 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 1 | 2023 |
| APPARATUS FOR LOW POWER TERNARY LOGIC CIRCUIT S Kim, SY Lee, S Park, S Kang US Patent App. 17/175,570, 2022 | | 2022 |
| TERNARY LOGIC CIRCUIT DEVICE S Kim, SY Lee, S Park, S Kang US Patent App. 17/489,629, 2022 | | 2022 |
| TERNARY LOGIC CIRCUIT DEVICE S Kim, SY Lee, S Park, S Kang US Patent 17/489,624, 2022 | | 2022 |
| APPARATUS AND METHOD FOR TERNARY LOGIC SYNTHESIS WITH MODIFIED QUINE-MCCLUSKEY ALGORITHM SY Lee, S Kim, S Kang US Patent 11,036,904, 2021 | | 2021 |
| Additive Statistical Leakage Analysis Using Exponential Mixture Model H Kwon, SY Lee, YH Kim, S Kang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | | 2020 |
Seokhyeong KangPohang University of Science and Technology (POSTECH)在 postech.ac.kr 的电子邮件经过验证
