标题/作者	年份
Chiplet heterogeneous integration technology—Status and challenges T Li, J Hou, J Yan, R Liu, H Yang, Z Sun Electronics 9 (4), 670	2020
2.3 a 220gops 96-core processor with 6 chiplets 3d-stacked on an active interposer offering 0.6 ns/mm latency, 3tb/s/mm 2 inter-chiplet interconnects and 156mw/mm [email protected] 82%-peak-efficiency dc-dc converters P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, G Moritz, I Miro-Panadès, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 46-48	2020
IntAct: A 96-core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, C Fuguet, I Miro-Panades, ... IEEE Journal of Solid-State Circuits 56 (1), 79-97	2020
A 1.02-pJ/b 20.83-Gb/s/wire USR transceiver using CNRZ-5 in 16-nm FinFET A Tajalli, MB Parizi, DA Carnelli, C Cao, K Gharibdoust, D Gorret, A Gupta, ... IEEE Journal of Solid-State Circuits 55 (4), 1108-1123	2020
A 14-GHz bang-bang digital PLL with sub-150-fs integrated jitter for wireline applications in 7-nm FinFET CMOS D Pfaff, R Abbott, XJ Wang, S Moazzeni, R Mason IEEE Journal of Solid-State Circuits 55 (3), 580-591	2019
Silicon-interconnect fabric for fine-pitch (≤ 10 μm) heterogeneous integration SC Jangam, SS Iyer IEEE Transactions on Components, Packaging and Manufacturing Technology 11 …	2021
SIAM: Chiplet-based scalable in-memory acceleration with mesh for deep neural networks G Krishnan, SK Mandal, M Pannala, C Chakrabarti, JS Seo, UY Ogras, ... ACM Transactions on Embedded Computing Systems (TECS) 20 (5s), 1-24	2021
8.3 a 3ghz arm neoverse n1 cpu in 7nm finfet for infrastructure applications R Christy, S Riches, S Kottekkat, P Gopinath, K Sawant, A Kona, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 148-150	2020
Design and analysis of logic-HBM2E power delivery system on CoWoS® platform with deep trench capacitor WT Chen, CC Lin, CH Tsai, H Hsia, KC Ting, SY Hou, CT Wang, D Yu 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 380-385	2020
NN-baton: DNN workload orchestration and chiplet granularity exploration for multichip accelerators Z Tan, H Cai, R Dong, K Ma 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …	2021
Heterogeneous power delivery for 7nm high-performance chiplet-based processors using integrated passive device and in-package voltage regulator A Roth, C Zhou, M Wong, E Soenen, TC Huang, P Ranucci, YC Hsu, ... 2020 IEEE Symposium on VLSI Technology, 1-2	2020
Streaming scan network (SSN): An efficient packetized data network for testing of complex SoCs JF Côté, M Kassab, W Janiszewski, R Rodrigues, R Meier, B Kaczmarek, ... 2020 IEEE International Test Conference (ITC), 1-10	2020
Ark: Fully homomorphic encryption accelerator with runtime data generation and inter-operation key reuse J Kim, G Lee, S Kim, G Sohn, M Rhu, J Kim, JH Ahn 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO …	2022
Low-temperature (260 C) solderless Cu–Cu bonding for fine-pitch 3-D packaging and heterogeneous integration H Park, H Seo, Y Kim, S Park, SE Kim IEEE Transactions on Components, Packaging and Manufacturing Technology 11 …	2021
A signaling figure of merit (s-FoM) for advanced packaging SC Jangam, SS Iyer IEEE Transactions on Components, Packaging and Manufacturing Technology 10 …	2020
Thermal-aware design space exploration of 3-d systolic ml accelerators R Mathur, AKA Kumar, L John, JP Kulkarni IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 7 …	2021
Design and development of high density fan-out wafer level package (HD-FOWLP) for deep neural network (DNN) chiplet accelerators using advanced interface bus (AIB) MD Rotaru, W Tang, D Rahul, Z Zhang 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 1258-1263	2021
Heterogeneous System-Level Package Integration—Trends and Challenges FJC Lee, M Wong, J Tzou, J Yuan, D Chang, S Rusu 2020 IEEE Symposium on VLSI Technology, 1-2	2020
Architecture of computing system based on chiplet G Shan, Y Zheng, C Xing, D Chen, G Li, Y Yang Micromachines 13 (2), 205	2022
A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2× 2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration U Rathore, SS Nagi, S Iyer, D Marković 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 52-54	2022

1 - 20

计算机程序会自动估算并确定日期和引用次数。