标题/作者	年份
Neuro-inspired computing with emerging nonvolatile memorys S Yu Proceedings of the IEEE 106 (2), 260-285	2018
Eyeriss v2: A flexible accelerator for emerging deep neural networks on mobile devices YH Chen, TJ Yang, J Emer, V Sze IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (2 …	2019
XNOR-SRAM: In-memory computing SRAM macro for binary/ternary deep neural networks S Yin, Z Jiang, JS Seo, M Seok IEEE Journal of Solid-State Circuits 55 (6), 1733-1743	2020
Circnn: accelerating and compressing deep neural networks using block-circulant weight matrices C Ding, S Liao, Y Wang, Z Li, N Liu, Y Zhuo, C Wang, X Qian, Y Bai, ... Proceedings of the 50th Annual IEEE/ACM International Symposium on …	2017
UNPU: A 50.6 TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision J Lee, C Kim, S Kang, D Shin, S Kim, HJ Yoo 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 218-220	2018
NullHop: A flexible convolutional neural network accelerator based on sparse representations of feature maps A Aimar, H Mostafa, E Calabrese, A Rios-Navarro, R Tapiador-Morales, ... IEEE transactions on neural networks and learning systems 30 (3), 644-656	2018
UNPU: An energy-efficient deep neural network accelerator with fully variable weight bit precision J Lee, C Kim, S Kang, D Shin, S Kim, HJ Yoo IEEE Journal of Solid-State Circuits 54 (1), 173-185	2018
A multi-functional in-memory inference processor using a standard 6T SRAM array M Kang, SK Gonugondla, A Patil, NR Shanbhag IEEE Journal of Solid-State Circuits 53 (2), 642-655	2018
A high energy efficient reconfigurable hybrid neural network processor for deep learning applications S Yin, P Ouyang, S Tang, F Tu, X Li, S Zheng, T Lu, J Gu, L Liu, S Wei IEEE Journal of Solid-State Circuits 53 (4), 968-982	2017
CONV-SRAM: An energy-efficient SRAM with in-memory dot-product computation for low-power convolutional neural networks A Biswas, AP Chandrakasan IEEE Journal of Solid-State Circuits 54 (1), 217-230	2018
A 64-tile 2.4-Mb in-memory-computing CNN accelerator employing charge-domain compute H Valavi, PJ Ramadge, E Nestler, N Verma IEEE Journal of Solid-State Circuits 54 (6), 1789-1799	2019
Embedded deep neural network processing: Algorithmic and processor techniques bring deep learning to iot and edge devices M Verhelst, B Moons IEEE Solid-State Circuits Magazine 9 (4), 55-65	2017
Admm-nn: An algorithm-hardware co-design framework of dnns using alternating direction methods of multipliers A Ren, T Zhang, S Ye, J Li, W Xu, X Qian, X Lin, Y Wang Proceedings of the Twenty-Fourth International Conference on Architectural …	2019
BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ... IEEE Journal of Solid-State Circuits 53 (4), 983-994	2017
Minimum energy quantized neural networks B Moons, K Goetschalckx, N Van Berckelaer, M Verhelst 2017 51st Asilomar Conference on Signals, Systems, and Computers, 1921-1925	2017
Efficient processing of deep neural networks V Sze, YH Chen, TJ Yang, JS Emer Synthesis Lectures on Computer Architecture 15 (2), 1-341	2020
A mixed-signal binarized convolutional-neural-network accelerator integrating dense weight storage and multiplication for reduced data movement H Valavi, PJ Ramadge, E Nestler, N Verma 2018 IEEE Symposium on VLSI Circuits, 141-142	2018
An architecture to accelerate convolution in deep neural networks A Ardakani, C Condo, M Ahmadi, WJ Gross IEEE Transactions on Circuits and Systems I: Regular Papers 65 (4), 1349-1362	2017
BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS B Moons, D Bankman, L Yang, B Murmann, M Verhelst 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4	2018
A variation-tolerant in-memory machine learning classifier via on-chip training SK Gonugondla, M Kang, NR Shanbhag IEEE Journal of Solid-State Circuits 53 (11), 3163-3173	2018

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