标题/作者	年份
{TVM}: An automated {End-to-End} optimizing compiler for deep learning T Chen, T Moreau, Z Jiang, L Zheng, E Yan, H Shen, M Cowan, L Wang, ... 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI …	2018
A configurable cloud-scale DNN processor for real-time AI J Fowers, K Ovtcharov, M Papamichael, T Massengill, M Liu, D Lo, ... 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …	2018
Bit fusion: Bit-level dynamically composable architecture for accelerating deep neural network H Sharma, J Park, N Suda, L Lai, B Chau, V Chandra, H Esmaeilzadeh 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …	2018
WRPN: Wide reduced-precision networks A Mishra, E Nurvitadhi, JJ Cook, D Marr arXiv preprint arXiv:1709.01134	2017
Apprentice: Using knowledge distillation techniques to improve low-precision network accuracy A Mishra, D Marr arXiv preprint arXiv:1711.05852	2017
FPGA-based accelerators of deep learning networks for learning and classification: A review A Shawahna, SM Sait, A El-Maleh ieee Access 7, 7823-7859	2018
Edge AI: On-demand accelerating deep neural network inference via edge computing E Li, L Zeng, Z Zhou, X Chen IEEE Transactions on Wireless Communications 19 (1), 447-457	2019
Circnn: accelerating and compressing deep neural networks using block-circulant weight matrices C Ding, S Liao, Y Wang, Z Li, N Liu, Y Zhuo, C Wang, X Qian, Y Bai, ... Proceedings of the 50th Annual IEEE/ACM International Symposium on …	2017
FP-BNN: Binarized neural network on FPGA S Liang, S Yin, L Liu, W Luk, S Wei Neurocomputing 275, 1072-1086	2018
An Always-On 3.8$\mu $ J/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28-nm CMOS D Bankman, L Yang, B Moons, M Verhelst, B Murmann IEEE Journal of Solid-State Circuits 54 (1), 158-172	2018
A survey of FPGA-based accelerators for convolutional neural networks S Mittal Neural computing and applications 32 (4), 1109-1139	2020
A survey of FPGA-based neural network accelerator K Guo, S Zeng, J Yu, Y Wang, H Yang arXiv preprint arXiv:1712.08934	2017
Binary neural networks: A survey H Qin, R Gong, X Liu, X Bai, J Song, N Sebe Pattern Recognition 105, 107281	2020
FINN-R: An end-to-end deep-learning framework for fast exploration of quantized neural networks M Blott, TB Preußer, NJ Fraser, G Gambardella, K O’brien, Y Umuroglu, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-23	2018
A high-throughput and power-efficient FPGA implementation of YOLO CNN for object detection DT Nguyen, TN Nguyen, H Kim, HJ Lee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (8 …	2019
Recent advances in efficient computation of deep convolutional neural networks J Cheng, P Wang, G Li, Q Hu, H Lu Frontiers of Information Technology & Electronic Engineering 19 (1), 64-77	2018
Toolflows for mapping convolutional neural networks on FPGAs: A survey and future directions SI Venieris, A Kouris, CS Bouganis arXiv preprint arXiv:1803.05900	2018
Deep neural network approximation for custom hardware: Where we've been, where we're going E Wang, JJ Davis, R Zhao, HC Ng, X Niu, W Luk, PYK Cheung, ... ACM Computing Surveys (CSUR) 52 (2), 1-39	2019
Accelerating CNN inference on FPGAs: A survey K Abdelouahab, M Pelcat, J Serot, F Berry arXiv preprint arXiv:1806.01683	2018
Admm-nn: An algorithm-hardware co-design framework of dnns using alternating direction methods of multipliers A Ren, T Zhang, S Ye, J Li, W Xu, X Qian, X Lin, Y Wang Proceedings of the Twenty-Fourth International Conference on Architectural …	2019

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