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h5 指数:29
h5 中位数:53

h5 指数是指在过去整整 5 年中所发表文章的 h 指数。h 指在 2018-2022 年间发表的 h 篇文章每篇至少都被引用过 h 次的最大值。隐藏

出版物的 h5 中位数，是指出版物的 h5 指数所涵盖的所有文章获得的引用次数的中位值。隐藏

标题/作者	引用次数	年份
An implantable 700μW 64-channel neuromodulation IC for simultaneous recording and stimulation with rapid artifact recovery BC Johnson, S Gambini, I Izyumin, A Moin, A Zhou, G Alexandrov, ... 2017 Symposium on VLSI Circuits, C48-C49	97	2017
BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ... 2017 Symposium on VLSI Circuits, C24-C25	79	2017
A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications S Yin, P Ouyang, S Tang, F Tu, X Li, L Liu, S Wei 2017 Symposium on VLSI Circuits, C26-C27	77	2017
A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory F Su, WH Chen, L Xia, CP Lo, T Tang, Z Wang, KH Hsu, M Cheng, JY Li, ... 2017 Symposium on VLSI Circuits, C260-C261	74	2017
A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS J Shen, A Shikata, L Fernando, N Guthrie, B Chen, M Maddox, ... 2017 Symposium on VLSI Circuits, C282-C283	73	2017
320× 240 Back-illuminated 10μm CAPD pixels for high speed modulation Time-of-Flight CMOS image sensor Y Kato, T Sano, Y Moriyama, S Maeda, T Yamazaki, A Nose, K Shina, ... 2017 Symposium on VLSI Circuits, C288-C289	70	2017
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM K Garello, F Yasin, H Hody, S Couet, L Souriau, SH Sharifi, J Swerts, ... 2019 Symposium on VLSI Circuits, T194-T195	69	2019
A 1V 0.25 uW inverter-stacking amplifier with 1.07 noise efficiency factor L Shen, N Lu, N Sun 2017 Symposium on VLSI Circuits, C140-C141	63	2017
A 3.43 TOPS/W 48.9 pJ/pixel 50.1 nJ/classification 512 analog neuron sparse coding neural network with on-chip learning and classification in 40nm CMOS FN Buhler, P Brown, J Li, T Chen, Z Zhang, MP Flynn 2017 Symposium on VLSI Circuits, C30-C31	62	2017
A 0.3 V VDDmin 4+ 2T SRAM for searching and in-memory computing using 55nm DDC technology Q Dong, S Jeloka, M Saligane, Y Kim, M Kawaminami, A Harada, ... 2017 Symposium on VLSI Circuits, C160-C161	61	2017
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing MS Lin, TC Huang, CC Tsai, KH Tam, CH Hsieh, T Chen, WH Huang, ... 2019 Symposium on VLSI Circuits, C28-C29	61	2019
A 1.06 μw smart ecg processor in 65 nm cmos for real-time biometric authentication and personal cardiac monitoring S Yin, M Kim, D Kadetotad, Y Liu, C Bae, SJ Kim, Y Cao, J Seo 2017 Symposium on VLSI Circuits, C102-C103	54	2017
Strong subthreshold current array PUF with 2 65 challenge-response pairs resilient to machine learning attacks in 130nm CMOS X Xi, H Zhuang, N Sun, M Orshansky 2017 Symposium on VLSI Circuits, C268-C269	53	2017
A 32Gb/s, 4.7 pJ/bit optical link with− 11.7 dBm sensitivity in 14nm FinFET CMOS J Proesel, Z Deniz, A Cevrero, I Ozkaya, S Kim, D Kuchta, S Lee, S Rylov, ... 2017 Symposium on VLSI Circuits, C318-C319	53	2017
An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier X Tang, B Kasap, L Shen, X Yang, W Shi, N Sun 2019 Symposium on VLSI Circuits, C140-C141	53	2019
A 5.1 pJ/Neuron 127.3 us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS R Guo, Y Liu, S Zheng, SY Wu, P Ouyang, WS Khwa, X Chen, JJ Chen, ... 2019 Symposium on VLSI Circuits, C120-C121	52	2019
A single-channel, 600Msps, 12bit, ringamp-based pipelined ADC in 28nm CMOS J Lagos, B Hershberg, E Martens, P Wambacq, J Craninckx 2017 Symposium on VLSI Circuits, C96-C97	51	2017
A 13b-ENOB 173dB-FoM 2 nd-order NS SAR ADC with passive integrators W Guo, H Zhuang, N Sun 2017 Symposium on VLSI Circuits, C236-C237	49	2017
Automotive LIDAR Technology ME Warren 2019 Symposium on VLSI Circuits, C254-C255	45	2019
A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell S Jeloka, K Yang, M Orshansky, D Sylvester, D Blaauw 2017 Symposium on VLSI Circuits, C270-C271	44	2017

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