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h5 指数:67
h5 中位数:87

h5 指数是指在过去整整 5 年中所发表文章的 h 指数。h 指在 2018-2022 年间发表的 h 篇文章每篇至少都被引用过 h 次的最大值。隐藏

出版物的 h5 中位数，是指出版物的 h5 指数所涵盖的所有文章获得的引用次数的中位值。隐藏

#2 Computer Hardware Design

标题/作者	引用次数	年份
14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI B Moons, R Uytterhoeven, W Dehaene, M Verhelst 2017 IEEE International Solid-State Circuits Conference (ISSCC), 246-247	372	2017
14.2 DNPU: An 8.1 TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks D Shin, J Lee, J Lee, HJ Yoo 2017 IEEE International Solid-State Circuits Conference (ISSCC), 240-241	274	2017
Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications A Biswas, AP Chandrakasan 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 488-490	246	2018
A 28GHz Bulk-CMOS dual-polarization phased-array transceiver with 24 channels for 5G user and basestation equipment JD Dunworth, A Homayoun, BH Ku, YC Ou, K Chakraborty, G Liu, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 70-72	235	2018
7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication B Sadhu, Y Tousi, J Hallin, S Sahl, S Reynolds, Ö Renström, K Sjögren, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 128-129	227	2017
An always-on 3.8 μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS D Bankman, L Yang, B Moons, M Verhelst, B Murmann 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 222-224	226	2018
A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors WH Chen, KX Li, WY Lin, KH Hsu, PY Li, CH Yang, CX Xue, EY Yang, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 494-496	215	2018
UNPU: A 50.6 TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision J Lee, C Kim, S Kang, D Shin, S Kim, HJ Yoo 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 218-220	214	2018
24.1 A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6 ns Parallel MAC Computing Time for CNN Based AI Edge Processors CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 388-390	179	2019
14.3 A 28nm SoC with a 1.2 GHz 568nJ/prediction sparse deep-neural-network engine with> 0.1 timing error rate tolerance for IoT applications PN Whatmough, SK Lee, H Lee, S Rama, D Brooks, GY Wei 2017 IEEE International Solid-State Circuits Conference (ISSCC), 242-243	170	2017
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors WS Khwa, JJ Chen, JF Li, X Si, EY Yang, X Sun, R Liu, PY Chen, Q Li, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 496-498	162	2018
A 42pJ/decision 3.12 TOPS/W robust in-memory machine learning classifier with on-chip training SK Gonugondla, M Kang, N Shanbhag 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 490-492	148	2018
9.5 An 80Gb/s 300GHz-Band Single-Chip CMOS Transceiver S Lee, R Dong, T Yoshida, S Amakawa, S Hara, A Kasamatsu, J Sato, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 170-172	144	2019
14.1 A 2.9 TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems G Desoli, N Chawla, T Boesch, S Singh, E Guidetti, F De Ambroggi, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 238-239	142	2017
24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398	140	2019
11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory C Kim, JH Cho, W Jeong, I Park, HW Park, DH Kim, D Kang, S Lee, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 202-203	139	2017
2.1 A 28GHz/37GHz/39GHz multiband linear Doherty power amplifier for 5G massive MIMO applications S Hu, F Wang, H Wang 2017 IEEE International Solid-State Circuits Conference (ISSCC), 32-33	131	2017
14.6 A 0.62 mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector K Bong, S Choi, C Kim, S Kang, Y Kim, HJ Yoo 2017 IEEE International Solid-State Circuits Conference (ISSCC), 248-249	126	2017
15.3 A 351TOPS/W and 372.4 GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications Q Dong, ME Sinangil, B Erbagci, D Sun, WS Khwa, HJ Liao, Y Wang, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 242-244	124	2020
16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology S Devarajan, L Singer, D Kelly, S Kosic, T Pan, J Silva, J Brunsilius, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 288-289	120	2017

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