| Optimization of 2.4 GHz CMOS low noise amplifier using hybrid particle swarm optimization with Lévy flight D Joshi, S Dash, A Malhotra, PV Sai, R Das, D Sharma, G Trivedi 2017 30th International Conference on VLSI Design and 2017 16th …, 2017 | 14 | 2017 |
| Multiobjective analog/RF circuit sizing using an improved brain storm optimization algorithm S Dash, D Joshi, G Trivedi Memetic Computing 10, 423-440, 2018 | 12 | 2018 |
| A hierarchy in mutation of genetic algorithm and its application to multi-objective analog/RF circuit optimization S Dash, D Joshi, A Sharma, G Trivedi Analog Integrated Circuits and Signal Processing 94, 27-47, 2018 | 11 | 2018 |
| Analog circuit optimization based on hybrid particle swarm optimization D Joshi, S Dash, U Agarwal, R Bhattacharjee, G Trivedi 2015 International Conference on Computational Science and Computational …, 2015 | 11 | 2015 |
| CMOS analog circuit optimization via river formation dynamics S Dash, D Joshi, G Trivedi 2016 26th International Conference Radioelektronika (Radioelektronika), 51-55, 2016 | 7 | 2016 |
| Minimizing area of VLSI power distribution networks using river formation dynamics S Dash, S Dey, D Joshi, G Trivedi Journal of Systems and Information Technology 20 (4), 417-429, 2018 | 6 | 2018 |
| Analog circuit optimization using adjoint network based sensitivity analysis D Joshi, S Dash, HS Jatana, R Bhattacharjee, G Trivedi AEU - International Journal of Electronics and Communications 82 (December …, 2017 | 3 | 2017 |
| A method of analog circuit optimization using adjoint sensitivity analysis D Joshi, S Dash, R Bhattacharjee, G Trivedi 2015 25th international conference Radioelektronika (RADIOELEKTRONIKA), 75-80, 2015 | 3 | 2015 |
| Hilbert-Huang Transform-Based Time-Frequency Analysis of Speech Signals for the Identification of Common Cold P Warule, SP Mishra, S Deb, D Joshi TENCON 2023-2023 IEEE Region 10 Conference (TENCON), 876-880, 2023 | 2 | 2023 |
| Multi-objective Hybrid Particle Swarm Optimization and its Application to Analog and RF Circuit Optimization D Joshi, S Dash, S Reddy, R Manigilla, G Trivedi Circuits, Systems, and Signal Processing 42 (8), 4443-4469, 2023 | 2 | 2023 |
| Mast cells in surgically resected appendices AA SHAH, M PATEL, R Jitendra, D JOSHI Medical Science 2 (7), 2013 | 2 | 2013 |
| Empirical Mode Decomposition Based Detection of Common Cold Using Speech Signal P Warule, SP Mishra, S Deb, D Joshi TENCON 2023-2023 IEEE Region 10 Conference (TENCON), 899-903, 2023 | 1 | 2023 |
| Performance investigation of source/drain extension region on nanosheet FET: A digital design perspective S Srivastava, S Panwar, M Shashidhara, N Bagga, D Joshi, A Acharya 2023 Silicon Nanoelectronics Workshop (SNW), 79-80, 2023 | 1 | 2023 |
| Bandgap engineering of earth-abundant Cu2BaSn (S1-xSex) 4 for photovoltaic application: A systematic approach to double grading HN Patel, RK Sharma, D Joshi, V Garg Solar Energy Materials and Solar Cells 269, 112792, 2024 | | 2024 |
| Elucidating the Potential Strategies for Performance Improvement of CBTSSe‐Based Solar Cells: A Pathway Toward 20% Efficiency HN Patel, RK Sharma, D Joshi, V Garg Energy Technology, 2301198, 2024 | | 2024 |
| Performance optimization of epitaxial-layer based Si/SiGe hetero-junction area scaled tunnel FET label-free biosensors considering steric hindrance S Panwar, S Srivastava, M Shashidhara, D Joshi, A Acharya Solid-State Electronics 210, 108810, 2023 | | 2023 |
| Rotating magnetic field configuration for controlled particle flux in material processing applications S Pandey, A Agarwal, D Joshi International Journal of Materials Research 114 (7-8), 746-750, 2023 | | 2023 |
| Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs S Panwar, S Srivastava, M Shashidhara, P Dubey, D Joshi, A Acharya 2023 Silicon Nanoelectronics Workshop (SNW), 81-82, 2023 | | 2023 |
| Configurable 8T SRAM-based Computing In-Memory Architecture for Enabling Shift Operation and Multibit Dot-Product Engines C Yeswanth, S Panwar, S Srivastava, D Joshi, M Shashidhara, A Acharya 2023 IEEE Devices for Integrated Circuit (DevIC), 330-334, 2023 | | 2023 |
| 9T SRAM Cell for Computation-In-Memory Architectures: Proposal & Investigation AK Gupta, P Joshi, S Srivastava, S Panwar, RS Shekhawat, AS Kilak, ... 2023 IEEE Devices for Integrated Circuit (DevIC), 282-286, 2023 | | 2023 |
Satyabrata DashPrincipal Engineer, TSMC在 iitg.ernet.in 的电子邮件经过验证
