Fan-out wafer-level packaging for heterogeneous integration
JH Lau, M Li, ML Qingqian, T Chen, I Xu… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
JH Lau, M Li, ML Qingqian, T Chen, I Xu, QX Yong, Z Cheng, N Fan, E Kuah, Z Li, KH Tan…
IEEE Transactions on Components, Packaging and Manufacturing …, 2018•ieeexplore.ieee.orgThe design, materials, process, fabrication, and reliability of a heterogeneous integration of
four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are
investigated in this paper. Emphasis is placed on the application of a new assembly process
for fabricating the redistribution layers of the FOWLP. Reliability assessments, such as the
thermal cycling and drop test, are also performed.
four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are
investigated in this paper. Emphasis is placed on the application of a new assembly process
for fabricating the redistribution layers of the FOWLP. Reliability assessments, such as the
thermal cycling and drop test, are also performed.
The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are investigated in this paper. Emphasis is placed on the application of a new assembly process for fabricating the redistribution layers of the FOWLP. Reliability assessments, such as the thermal cycling and drop test, are also performed.
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