Low power and high speed sample-and-hold circuit

R Trivedi - 2006 49th IEEE International Midwest Symposium …, 2006 - ieeexplore.ieee.org
This paper describes the improved sample-and-hold architecture as a front-end block of low
power and high speed pipelined analog to digital converter. The circuit consists of bottom …
被引用次数：26 相关文章

Low power and high speed sample and hold circuit

R Trivedi - 2006 - 14.139.122.115
In this thesis work the design of a high speed and low power CMOS sample and hold circuit
as a front-end block of pipelined analog-to-digital converter is described. The circuit consists …

Low power and high speed sample and hold circuit

R Trivedi - 2006 - drsr.daiict.ac.in
In this thesis work the design of a high speed and low power CMOS sample and hold circuit
as a front-end block of pipelined analog-to-digital converter is described. The circuit consists …

Low Power and High Speed Sample-and-Hold Circuit

R Trivedi - 2006 49th IEEE International Midwest Symposium on … - infona.pl
This paper describes the improved sample-and-hold architecture as a front-end block of low
power and high speed pipelined analog to digital converter. The circuit consists of bottom …