12 bits, 40MS/s, low power pipelined SAR ADC
VK Lazarjan, K Hajsadeghi - 2014 IEEE 57th International …, 2014 - ieeexplore.ieee.org
VK Lazarjan, K Hajsadeghi
2014 IEEE 57th International Midwest Symposium on Circuits and …, 2014•ieeexplore.ieee.orgThis paper presents a low power SAR ADC utilizing pipelining to increase the resolution up
to 12 bits while maintaining a high speed sampling rate. Novel system level modifications
and also new comparator architecture are proposed to optimize the power consumption. The
ADC is designed and simulated in 0.18 um CMOS technology by 1.2 v supply voltage
consuming 4.5 mW power at 40MS/s sampling rate. The results indicates an effective
number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which …
to 12 bits while maintaining a high speed sampling rate. Novel system level modifications
and also new comparator architecture are proposed to optimize the power consumption. The
ADC is designed and simulated in 0.18 um CMOS technology by 1.2 v supply voltage
consuming 4.5 mW power at 40MS/s sampling rate. The results indicates an effective
number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which …
This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method.
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