16.1 A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices
CX Xue, JM Hung, HY Kao, YH Huang… - … Solid-State Circuits …, 2021 - ieeexplore.ieee.org
2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021•ieeexplore.ieee.org
Battery-powered tiny-AI edge devices require large-capacity nonvolatile compute-in-memory
(nvCIM), with multibit input (IN), weight (W), and output (OUT) precision to support complex
applications, high-energy efficiency (EF MAC), and short computing latency (t AC) for
multiply-and-accumulate (M AC) operations. Due to the low read-disturb-free voltage of
nonvolatile memory (NVM) devices and the large parasitic load on the bitline, most existing
Mb-level nvCIM macros use a current-mode read scheme [1-5] and only achieve a low IN-W …
(nvCIM), with multibit input (IN), weight (W), and output (OUT) precision to support complex
applications, high-energy efficiency (EF MAC), and short computing latency (t AC) for
multiply-and-accumulate (M AC) operations. Due to the low read-disturb-free voltage of
nonvolatile memory (NVM) devices and the large parasitic load on the bitline, most existing
Mb-level nvCIM macros use a current-mode read scheme [1-5] and only achieve a low IN-W …
Battery-powered tiny-AI edge devices require large-capacity nonvolatile compute-in-memory (nvCIM), with multibit input (IN), weight (W), and output (OUT) precision to support complex applications, high-energy efficiency (EF MAC ), and short computing latency (t AC ) for multiply-and-accumulate (M AC ) operations. Due to the low read-disturb-free voltage of nonvolatile memory (NVM) devices and the large parasitic load on the bitline, most existing Mb-level nvCIM macros use a current-mode read scheme [1-5] and only achieve a low IN-W precision (binary to 4b).
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