An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in
this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature
sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over
4-8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase
detection scheme enabling continuous data rate support. The digital architecture not only
eliminates the large filtering capacitor but also makes the design more tolerant to process …

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in
this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature
sampling clocks from 4 to 8 GHz. A new, low-power and two-step PI with high linearity over 4-
8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase
detection scheme, which enables continuous data rate support. The digital architecture not
only eliminates the large filtering capacitor, but also makes the design more tolerant to …