This paper describes the design of a 10-Gb/s fully integrated CMOS optical receiver, which consists of a novel spatially-modulated photo detector (SMPD), a low-noise trans-impedance amplifier (TIA), and a post-limiting amplifier on a single chip. The bandwidth of proposed meshed SMPD can be boosted up to 6.9 GHz under a reverse-biased voltage of 14.2 V. The measured responsivity of the meshed SMPD is 29 mA/W as illuminated by 850-nm light source. To compensate the relatively low responsivity of on-chip CMOS photo detector (PD), a high-gain TIA with nested feedback and shunt peaking is proposed to achieve low-noise operation. The optical receiver is capable of delivering 25-kΩ conversion gain when driving 50-Ω output loads. For a PRBS test pattern of 2 ⁷ - 1, the 10-Gb/s optoelectronic integrated circuit (OEIC) has optical sensitivity of - 6 dBm at a bit-error rate (BER) of 10 ^-11 . Implemented in a generic 0.18-μm CMOS technology, the chip area is 0.95 mm by 0.8 mm. The trans-impedance amplifier, post amplifier, and output buffer respectively drain 38 mW, 80 mW, and 27 mW from the 1.8-V supply.