A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones

RB Staszewski, CM Hung, N Barton… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
RB Staszewski, CM Hung, N Barton, MC Lee, D Leipold
IEEE Journal of Solid-State Circuits, 2005ieeexplore.ieee.org
We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular
mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver
realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is
achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices
that operate in flat regions of their CV curves. The varactors are partitioned into binary-
weighted and unit-weighted banks that are sequentially activated during frequency locking …
We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C- V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order /spl Sigma//spl Delta/ dithering. We analyze the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the /spl Sigma//spl Delta/ dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation.
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