A discrete-time bluetooth receiver in a 0.13/spl mu/m digital cmos process
K Muhammad, D Leipold, B Staszewski… - … Solid-State Circuits …, 2004 - ieeexplore.ieee.org
2004 IEEE International Solid-State Circuits Conference (IEEE Cat …, 2004•ieeexplore.ieee.org
A discrete-time receiver architecture for a wireless application is presented. Analog signal
processing concepts are used to directly sample the RF input at Nyquist rate. Maximum
receiver sensitivity is-83dBm and the chip consumes a total of 41mA from a 1.575 V
internally regulated supply. The receiver is implemented in a 0.13/spl mu/m digital CMOS
process.
processing concepts are used to directly sample the RF input at Nyquist rate. Maximum
receiver sensitivity is-83dBm and the chip consumes a total of 41mA from a 1.575 V
internally regulated supply. The receiver is implemented in a 0.13/spl mu/m digital CMOS
process.
A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13/spl mu/m digital CMOS process.
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