This paper describes a low power low offset CMOS front-end amplifier for portable EEC acquisition system. The proposed EEG front-end amplifier consists of a high pass filter, low noise pre-amplification stage with nested choppers, 5/sup th/-order tuneable low pass filter and programmable gain instrumentation amplification stage. With the high pass filter embedded in the outer choppers, both inherent DC offset from the EEG signal and intrinsic offsets from the high pass filter and preamplifier can be effectively removed. The front-end amplifier features a simulated input referred offset of less than 0.2 /spl mu/V and a maximum amplification of 83.5 dB without saturating the intermediate stages. Under a 2.65-V supply, it consumes 476 /spl mu/W. The chip design is based on a 0.35-/spl mu/m CMOS technology and occupies a die area of 0.9264 mm/sup 2/.