… , we propose two asymmetric FinFET based SRAM cells that are … SRAM array is good for
designing low power and robust caches, while the ADWL cache is appropriate for low power …

… hierarchy computing system. Static Random Access Memory (SRAM) is mainly used among
all the memory types; SRAMs … various parameters of both FinFET based SRAM cells at 16nm …

… well tempered undoped ultra thin body FinFETs can lead to ultra low power SRAM arrays. …
of 4T-FinFET based source-biased SRAM in embedded memory hierarchy. We conclude that …

… This paper presents a single-ended low-power 7T SRAM cell … comparison with the conventional
8T SRAM cell. By using only … Static noise margins of the FinFET-based SRAM cells at V …

… FinFET-based SRAM has less power consumption and area but a delay is more than 22
nm. Hierarchical FinFET SRAM is … low-power techniques that are utilized to attain low-power …

… The SRAM memory is designed for low-power applications by using a … (CAM) using pipelined
hierarchical search scheme. IEEE … SOI FinFET based 10T SRAM cell design against short …

… We explore the hybrid style hierarchically. We first use it to design various CPU modules,
eg, execution units, SRAMs, and caches. We have developed 22nm FinFET logic libraries …

… as secondary storage in the hierarchy of computer storage. However… This section describes
the FinFET based SRAM cell … of the behaviour of FinFET based SRAM when low power, high …

… designing low-power and robust FinFET based SRAM cell is a major challenge in nanoscale
technologies. Process … [9] BD Yang and LS Kim, “A low-power SRAM using hierarchical bit …

… The ultra-low-power design becomes an emerging … chain adders (MCC) in a hierarchal
approach. Carry select adder (CSA) … Similarly, the SRAM and Register blocks show a reduction of …