In nanometer-scale VLSI physical design, clock tree becomes a major concern on
determining the total performance of the chip. Both the clock skew and the PVT (process,
voltage and temperature) variations contribute a lot to the behavior of the digital circuits.
Previous works mainly focused on skew and wirelength minimization. However, it may lead
to negative influence on the variation factors. In this paper, a novel clock tree synthesizer is
proposed for performance improvement. Several algorithms are introduced to tackle the …