Applications of a CMOS current squaring circuit in analog signal processing
2015 38th International Conference on Telecommunications and …, 2015•ieeexplore.ieee.org
Applications of a CMOS squaring circuit in analog signal processing is studied in this paper.
The circuit is based on the dual translinear loop and square-law characteristic of MOS
transistor in saturation region. The reconfigurable circuit is employed as a basic analog cell
for the implementation of several building blocks including multiplier, logarithmic, divider
and exponential function generator circuits. It is proposed a solution for implamentation of
the analog logarithmic and exponential functions, which are not an easily accessible …
The circuit is based on the dual translinear loop and square-law characteristic of MOS
transistor in saturation region. The reconfigurable circuit is employed as a basic analog cell
for the implementation of several building blocks including multiplier, logarithmic, divider
and exponential function generator circuits. It is proposed a solution for implamentation of
the analog logarithmic and exponential functions, which are not an easily accessible …
Applications of a CMOS squaring circuit in analog signal processing is studied in this paper. The circuit is based on the dual translinear loop and square-law characteristic of MOS transistor in saturation region. The reconfigurable circuit is employed as a basic analog cell for the implementation of several building blocks including multiplier, logarithmic, divider and exponential function generator circuits. It is proposed a solution for implamentation of the analog logarithmic and exponential functions, which are not an easily accessible characteristic in CMOS technology, as well as their integration in a configurable cell. Current-mode implementation of the circuits leads to straightforward and intuitive configurations. To study the performance of the circuit, effects of channel-length modulation as well as the mismatch in the threshold voltages are thoroughly discussed. The proposed circuits are designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 μm standard CMOS technology. MATLAB results validate the simulation results which are obtained by HSPICE.
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