Bottom pinned SOT-MRAM bit structure and method of fabrication

PM Braganca, H Tseng, L Wan - US Patent 9,768,229, 2017 - Google Patents
Embodiments of the present disclosure generally relate to data storage and computer
memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM
chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of
transistors. The leads may be made of a material having large spin-orbit coupling strength
and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first
portions and a plurality of second portions distinct from the first portions. The electrical …

Bottom pinned SOT-MRAM bit structure and method of fabrication

PM Braganca, H Tseng, L Wan - US Patent 10,490,601, 2019 - Google Patents
Embodiments of the present disclosure generally relate to data storage and computer
memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM
chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of
transistors. The leads may be made of a material having large spin-orbit coupling strength
and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first
portions and a plurality of second portions distinct from the first portions. The electrical …
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