In SRAM cell design, the energy consumption and cell stability are the major performance indices which need to be improved. Several techniques reported earlier attempt to improve either of the stability or the energy consumption. In this paper, a scheme is proposed which uses current starving on conventional SRAM cell to improve cell stability and also to reduce energy consumption. Unlike separating the read and write port of the SRAM cell in most of the techniques proposed earlier, this technique results more ideal voltage transfer characteristic of the cross-coupled inverter leading to larger noise margin. It also reduces the dynamic energy consumption through short circuit current reduction during state transition. The proposed technique is compared with NC-SRAM [3], IWLVC-SRAM [18], 10T-SRAM [16] and a conventional 6T-SRAM cell. The read and retention stability of the current starving SRAM (CS-SRAM) cell increases by 31 and 41%, respectively, with respect to the 6T-RAM cell. These two SNMs are also significantly higher than the other compared cells. The proposed technique consumes 22% lesser energy in comparison with the 6T-SRAM. The energy consumption is also reduced in comparison with the other compared cells. The compared cells are designed both in CMOS process and in FinFET technology (20 nm PTM library). The performance enhancement of the proposed cell maintains same trend in both technologies.