Design of a low power flip-flop using CMOS deep sub micron technology
S Naik, R Chandel - 2010 International Conference on Recent …, 2010 - ieeexplore.ieee.org
This paper enumerates low power, high speed design of flip-flop having less number of
transistors and only one transistor being clocked by short pulse train which is true single
phase clocking (TSPC) flip-flop. Compared to Conventional flip-flop, it has 5 Transistors and
one transistor clocked, thus has lesser size and lesser power consumption. It can be used in
various applications like digital VLSI clocking system, buffers, registers, microprocessors etc.
The analysis for various flip flops and latches for power dissipation and propagation delays …
transistors and only one transistor being clocked by short pulse train which is true single
phase clocking (TSPC) flip-flop. Compared to Conventional flip-flop, it has 5 Transistors and
one transistor clocked, thus has lesser size and lesser power consumption. It can be used in
various applications like digital VLSI clocking system, buffers, registers, microprocessors etc.
The analysis for various flip flops and latches for power dissipation and propagation delays …
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