As Moore's Law scaling tapers off, there is a growing emphasis on improving the energy-efficiency of nanometer ICs through architectural techniques. Recently, approximate computing has been introduced to address the energy-efficiency problems of error tolerant applications in all forms of computing from mobile IoT devices to datacenters and servers. This technique has proved successful in various application domains such as digital signal processing, deep machine learning, and combinatorial optimization. Approximate computing trades accuracy for power, delay, and area in computing systems. One key arithmetic circuit in digital signal processing is multi-bit digital adder that is widely used in today's user applications. Adders consume significant amounts of system energy and occupy large portions of the processor die area. The need for low power and high-speed circuits as well as the error-resiliency of the digital signal processing systems allow the system designers to innovate energy-efficient approximate adders. This paper examines DrAx, a design remedy for approximation, which provides an automatic method to improve the accuracy of approximate adders with virtually no impact on their power and area consumption. The proposed method is applied to seven state-of-the-art approximate adders for evaluation; our simulation results indicate 12–50% accuracy regarding mean error distance metric improvements are attainable for the baseline approximate adders using the proposed design approach.