Evaluation of level-shifted and phase-shifted PWM schemes for seven level single-phase packed U cell inverter
CPSS Transactions on Power Electronics and Applications, 2018•ieeexplore.ieee.org
An evaluation of level shifted and phase shifted triangular and sawtooth carrier modulation
schemes for a seven level packed U cell (PUC) inverter is presented in this paper. The
investigated PUC is the recently introduced topology for multilevel inverter having reduced
switch count in comparison to the conventional topologies of multilevel inverters. The PUC
inverter has six switches for 7 level inverter which is very less in comparison to the
conventional topologies. In this paper, the level-shifted pulse width modulation (LS-PWM) …
schemes for a seven level packed U cell (PUC) inverter is presented in this paper. The
investigated PUC is the recently introduced topology for multilevel inverter having reduced
switch count in comparison to the conventional topologies of multilevel inverters. The PUC
inverter has six switches for 7 level inverter which is very less in comparison to the
conventional topologies. In this paper, the level-shifted pulse width modulation (LS-PWM) …
An evaluation of level shifted and phase shifted triangular and sawtooth carrier modulation schemes for a seven level packed U cell (PUC) inverter is presented in this paper. The investigated PUC is the recently introduced topology for multilevel inverter having reduced switch count in comparison to the conventional topologies of multilevel inverters. The PUC inverter has six switches for 7 level inverter which is very less in comparison to the conventional topologies. In this paper, the level-shifted pulse width modulation (LS-PWM) and phase-shifted PWM (PS-PWM) for triangular and sawtooth carrier are presented and compared. A comparative harmonic analysis for all the cases is performed and results are presented in the paper. The difference in harmonics of the two modulation methods given by the theoretical approach for both the carrier is validated by the experimental results. DC voltage controller and load current controller of the PUC inverter are also designed and presented. The investigated PUC topology is tested in dynamic and steady state conditions and results obtained are presented. The analysis is done and validated using simulation in MATLAB Simulink environment and experimental approaches using FPGA platform.
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