This paper investigates a reduced switch count topology for seven-level single-phase voltage-source inverter, nomenclatures as asymmetrical holding capacitor or also known as asymmetrical flying level capacitor or packed U-cell (PUC). Modular configuration of the inverter consists of one U-cell, four additional power switches, and one dc link. U-cell network is an arrangement of two semiconductor switches with one holding or clamping capacitor. Topology offers a reduced switch count solution with simple control strategy compared to the existing seven-level inverters. Different standard multicarrier sinusoidal pulse-width modulation techniques (SPWMs) are adapted for the generation of switching gate signals for the PUC power switches, and these SPWMs are compared with novel optimization-based selective harmonic elimination (SHE) that employs genetic algorithm (GA) for solving nonlinear SHE equation with a constraint that eliminated all third-order harmonics efficiently. The investigation that involves analysis and comparison is done for obtaining reduced total harmonic distortion (THD) by using different level-shifted multicarrier SPWM schemes along with proposed GA-based SHE. Obtained findings with design of dc voltage and load current controllers are elaborated and presented in this paper. For better understanding, the converter topology is tested under different dynamic conditions. Mathematical background developed on the theoretical basis is verified by numerical simulation software and also validated on the developed laboratory-scale prototype experimental setup.