In this paper we propose a novel and efficient hardware implementation of an image watermarking system based on the Haar Discrete Wavelet Transform (DWT). DWT is used in image watermarking to hide secret pieces of information into a digital content with a good robustness. The main advantage of Haar DWT is the frequencies separation into four subbands (LL, LH, HL, and HH) which can be treated independently. This permits ensuring a better compromise between robustness and visibility factors. A Field Programmable Gate Array (FPGA) that is based on a very large scale integration architecture of the watermarking algorithm is developed to accelerate media authentication. A hardware cosimulation strategy using the Matlab‐Xilinx system generator (XSG) was applied to prove the validity of the suggested implementation. The hardware cosimulation results show the effectiveness of the developed architecture in terms of visibility and robustness against several attacks. The proposed hardware system presents also a high performance in terms of the operating speed.