In the present work, a fast square root algorithm with tunable accuracy has been developed to minimise the number of clock pulses to compute an accurate square root value with a low hardware complexity. The proposed method uses a binomial expansion series guided initial guess to converge faster and thus reduces the number of iterations required to get to the square root value. It also allows the user to modulate the amount of accuracy required by changing the number of iterations and balance the accuracy with the time required to compute the square root value. The proposed architecture is synthesised on a Xilinx xC6vlx75t-2ff1784 family of FPGA and the device utilisation summary is analysed and compared to that of the other recently introduced algorithms. The simulation results are obtained on ModelSim 10.5c (Quartus Prime Pro 17.0) using Verilog programming Language.