Hardware evolution at function level
M Murakawa, S Yoshizawa, I Kajitani, T Furuya… - Parallel Problem Solving …, 1996 - Springer
This paper describes a function-level Evolvable Hardware (EHW). EHW is hardware which
is built on programmable logic devices (eg PLD and FPGA) and whose architecture can be
reconfigured by using a genetic learning to adapt to new unknown environments in real
time. It is demonstrated that the function-level hardware evolution can attain much higher
performances than the gate-level evolution, in neural network applications (eg two-spiral).
VLSI architecture of the functionbased FPGA dedicated to function level evolution is also …
is built on programmable logic devices (eg PLD and FPGA) and whose architecture can be
reconfigured by using a genetic learning to adapt to new unknown environments in real
time. It is demonstrated that the function-level hardware evolution can attain much higher
performances than the gate-level evolution, in neural network applications (eg two-spiral).
VLSI architecture of the functionbased FPGA dedicated to function level evolution is also …
Hardware evolution at function level
M Iwata, I Kajitani, T Furuya, S Yoshizawa, T Higuchi… - (No Title), 1996 - cir.nii.ac.jp
This paper describes a function-level Evolvable Hardware (EHW). EHW is hardware which
is built on programmable logic devices (eg PLD and FPGA) and whose architecture can be
reconfigured by using a genetic learning to adapt to new unknown environments in real
time. It is demonstrated that the function-level hardware evolution can attain much higher
performances than the gate-level evolution, in neural network applications (eg two-spiral).
VLSI architecture of the functionbased FPGA dedicated to function level evolution is also …
is built on programmable logic devices (eg PLD and FPGA) and whose architecture can be
reconfigured by using a genetic learning to adapt to new unknown environments in real
time. It is demonstrated that the function-level hardware evolution can attain much higher
performances than the gate-level evolution, in neural network applications (eg two-spiral).
VLSI architecture of the functionbased FPGA dedicated to function level evolution is also …
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