Hardware optimization for belief propagation polar code decoder with early stopping criteria using high-speed parallel-prefix ling adder
2017 40th International Conference on Telecommunications and …, 2017•ieeexplore.ieee.org
Belief propagation (BP) polar code decoder is well-studied from many aspects. This study
proposes a hardware optimization to improve performance of polar BP decoder by modifying
both processing element (PE) and early stopping criterion (ESC). PE is optimized by using
high-speed parallel-prefix Ling adder instead of carry ripple adder and WIB ESC introduced
in literature is optimized by removing unnecessary adder array. FPGA implementation is
made to verify the idea behind this study. The results show that throughput of polar code …
proposes a hardware optimization to improve performance of polar BP decoder by modifying
both processing element (PE) and early stopping criterion (ESC). PE is optimized by using
high-speed parallel-prefix Ling adder instead of carry ripple adder and WIB ESC introduced
in literature is optimized by removing unnecessary adder array. FPGA implementation is
made to verify the idea behind this study. The results show that throughput of polar code …
Belief propagation (BP) polar code decoder is well-studied from many aspects. This study proposes a hardware optimization to improve performance of polar BP decoder by modifying both processing element (PE) and early stopping criterion (ESC). PE is optimized by using high-speed parallel-prefix Ling adder instead of carry ripple adder and WIB ESC introduced in literature is optimized by removing unnecessary adder array. FPGA implementation is made to verify the idea behind this study. The results show that throughput of polar code belief propagation decoder can be increase significantly by using proposed approach. More accurate comparison can be made by application specific chip design with same parameters. This part of the study will be held in future.
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