Ternary logic is a promising alternative to the conventional binary logic in VLSI design as it
provides the advantages of reduced interconnects, higher operating speeds, and smaller
chip area. This paper presents a pair of circuits for implementing a ternary half adder using
carbon nanotube field-effect transistors. The proposed designs combine both futuristic
ternary and conventional binary logic design approach. One of the proposed circuits for
ternary to binary decoder simplifies further circuit implementation and provides excellent …

This paper presents two new designs to implement a ternary half adder using Carbon
Nanotubes Field Effect Transistors (CNFETs). Ternary logic is a promising alternative to
conventional binary logic, since it is possible to accomplish simplicity and energy efficiency
in modern digital design due to reduced circuit overhead such as interconnect and chip
area. In this paper the authors are presenting two different novel ternary half adder circuits
using ternary decoders and binary logic gates. The circuits are simulated using HSPICE to …