We propose a novel dissipation scheme for level-set based wet etching simulations. The scheme enables modeling of the temporal evolution of the etch profile during anisotropic wet etching processes and is based on the local geometry and the crystallographic direction-dependent etch rate. We implemented the scheme into Silvaco's Victory Process simulator which is utilized in this work to simulate the fabrication of source/drain cavities for sub-28 nm strained metal-oxide-semiconductor fieldeffect transistors. Our results show excellent agreement with experimental data. In particular, the main cavity-related design variables are accurately predicted.