A widely used technique to mitigate gate leakage in ultrascaled metal oxide semiconductor field effect transistors ( mosfets) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as SiO ₂ , but thicker physical layers. However, using a thicker physical dielectric for the same EOT has a negative effect on the device performance due to the degradation of 2D electrostatics. In this paper, the effects of high-k oxides on double-gate (DG) mosfet with gate length under 20 nm are studied. All the devices are modeled using an effective mass quantum transport approach based on the quantum transmitting boundary method, where only ballistic transport is considered. We find that there is an optimum physical oxide thickness (T _OX ) to achieve the best performance in terms of on-current for each gate stack, including SiO ₂ interface layer and one high-k material. For the same EOT, Al ₂ O ₃ (k = 9) over 3-Å SiO ₂ provides the best performance, while for HfO ₂ (k = 22) and La ₂ O ₃ (k = 30), SiO ₂ thicknesses should be 5 Å and 7 Å, respectively. The effects of using high-k oxides and gate stacks on the performance of ultrascaled mosfets are analyzed. While thin oxide thickness increases the gate leakage, the thick oxide layer reduces the gate control on the channel. Therefore, the physical thicknesses of gate stack should be optimized to achieve the best performance.