Performance analysis of a Ge/Si core/shell nanowire field-effect transistor

G Liang, J Xiang, N Kharche, G Klimeck, CM Lieber… - Nano …, 2007 - ACS Publications
G Liang, J Xiang, N Kharche, G Klimeck, CM Lieber, M Lundstrom
Nano letters, 2007ACS Publications
We ana/lyze the performance of a recently reported Ge/Si core/shell nanowire transistor
using a semiclassical, ballistic transport model and an sp3d5s* tight-binding treatment of the
electronic structure. Comparison of the measured performance of the device with the effects
of series resistance removed to the simulated result assuming ballistic transport shows that
the experimental device operates between 60 and 85% of the ballistic limit. For this∼ 15 nm
diameter Ge nanowire, we also find that 14− 18 modes are occupied at room temperature …
We ana/lyze the performance of a recently reported Ge/Si core/shell nanowire transistor using a semiclassical, ballistic transport model and an sp3d5s* tight-binding treatment of the electronic structure. Comparison of the measured performance of the device with the effects of series resistance removed to the simulated result assuming ballistic transport shows that the experimental device operates between 60 and 85% of the ballistic limit. For this ∼15 nm diameter Ge nanowire, we also find that 14−18 modes are occupied at room temperature under ON-current conditions with ION/IOFF = 100. To observe true one-dimensional transport in a ⟨110⟩ Ge nanowire transistor, the nanowire diameter would have to be less than about 5 nm. The methodology described here should prove useful for analyzing and comparing on a common basis nanowire transistors of various materials and structures.
ACS Publications
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