The present paper proposes a secure design of the energy-efficient multi-modular exponential techniques that use store and reward method and store and forward method. Computation of the multi-modular exponentiation can be performed by three novel algorithms: store and reward, store and forward 1-bit (SFW1), and store and forward 2-bit (SFW2). Hardware realizations of the proposed algorithms are analyzed in terms of throughput and energy. The experimental results show the proposed algorithms SFW1 and SFW2 increase the throughput by orders of 3.98% and 4.82%, reducing the power by 5.32% and 6.15% and saving the energy in the order of 3.95% and 4.75%, respectively. The proposed techniques can prevent possible side-channel attacks and timing attacks as a consequence of an inbuilt confusion mechanism. Xilinx Vivado-21 on Virtex-7 evaluation board and integrated computer application for recognizing user services (ICARUS) Verilog simulation and synthesis tools are used for field programmable gate array (FPGA) for hardware realization. The hardware compatibility of proposed algorithms has also been checked using Cadence for application specific integrated circuit (ASIC).