Sniper: Scalable and accurate parallel multi-core simulation
Sniper is a next generation parallel, high-speed and accurate x86 simulator. This multi-core
simulator is based on the interval core model and the Graphite simulation infrastructure,
allowing for fast and accurate simulation and for trading off simulation speed for accuracy to
allow a range of flexible simulation options when exploring different homogeneous and
heterogeneous multi-core architectures. The Sniper simulator allows one to perform timing
simulations for both multi-programmed workloads and multi-threaded, shared-memory …
simulator is based on the interval core model and the Graphite simulation infrastructure,
allowing for fast and accurate simulation and for trading off simulation speed for accuracy to
allow a range of flexible simulation options when exploring different homogeneous and
heterogeneous multi-core architectures. The Sniper simulator allows one to perform timing
simulations for both multi-programmed workloads and multi-threaded, shared-memory …
[PDF][PDF] Sniper: Scalable and accurate parallel multi-core simulation
ABSTRACT The Intel ExaScience Lab in Leuven, Belgium focuses on accurate space
weather modeling, extremely scalable fault-tolerant simulation toolkits, in situ visualization
through virtual telescopes, and architectural simulation of large-scale systems and
workloads. This article describes recent advances achieved in the lab in architectural
simulation of individual nodes in the Exascale era. Two major trends in high-performance
computing, namely, larger numbers of cores and the growing size of on-chip cache memory …
weather modeling, extremely scalable fault-tolerant simulation toolkits, in situ visualization
through virtual telescopes, and architectural simulation of large-scale systems and
workloads. This article describes recent advances achieved in the lab in architectural
simulation of individual nodes in the Exascale era. Two major trends in high-performance
computing, namely, larger numbers of cores and the growing size of on-chip cache memory …
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