The (static random access memory) SRAM cell plays an important role to design a balanced and optimized processor for cache memory. Typically, the primary 6T SRAM cell gives more power loss and delay. To reduce the total power and static power loss, the N-Controlled(NC) and 8T cells are designed. However, due to extra added transistors, the NC and 8T cells consume more area and give less stability. The new 5T SRAM cell has been proposed to overcome these problems. The proposed cell consumes 7.5%, 20.0%, and 20.12% less area in comparison of 6T, NC, and 8T cell, respectively. The total power loss of the proposed 5T cell is decreased by 90.62%, 86.29%, and 84.07% compared to 6T, NC, and 8T, respectively. Similarly, the static power loss of the proposed cell is reduced by 75.78%, 49.07%, and 70.82% compared to 6T, NC, and 8T, respectively. The speed is improved by 50.54%, 48.82%, and 43.87% compared to 6T, NC, and 8T, respectively. The stability of the proposed cell is comparable. The Monte Carlo (MC) simulation with process variations for the proposed cell has been performed to check the deviation.