The first fully integrated quad-band GSM/GPRS receiver in a 90-nm digital CMOS process
K Muhammad, YC Ho, TL Mayhugh… - IEEE Journal of Solid …, 2006 - ieeexplore.ieee.org
K Muhammad, YC Ho, TL Mayhugh, CM Hung, T Jung, I Elahi, C Lin, I Deng, C Fernando…
IEEE Journal of Solid-State Circuits, 2006•ieeexplore.ieee.orgWe present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full
integration of quad-band receiver, transmitter, memory, power management, dedicated ARM
processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses
Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for
generating the local oscillator (LO). The receive chain uses discrete-time analog signal
processing to down-convert, down-sample, filter and analog-to-digital convert the received …
integration of quad-band receiver, transmitter, memory, power management, dedicated ARM
processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses
Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for
generating the local oscillator (LO). The receive chain uses discrete-time analog signal
processing to down-convert, down-sample, filter and analog-to-digital convert the received …
We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of -110 dBm at 60mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates
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