The microarchitecture of the synergistic processor for a cell processor
B Flachs, S Asano, SH Dhong… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
B Flachs, S Asano, SH Dhong, HP Hofstee, G Gervais, R Kim, T Le, P Liu, J Leenstra…
IEEE Journal of Solid-State Circuits, 2005•ieeexplore.ieee.orgThis paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k
process. The dual-issue, four-way SIMD processor emphasizes achievable performance per
area and power. Software controls most aspects of data movement and instruction flow to
improve memory system performance and core performance density. The design minimizes
instruction latency while providing for fine grain clock control to reduce power.
process. The dual-issue, four-way SIMD processor emphasizes achievable performance per
area and power. Software controls most aspects of data movement and instruction flow to
improve memory system performance and core performance density. The design minimizes
instruction latency while providing for fine grain clock control to reduce power.
This paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k process. The dual-issue, four-way SIMD processor emphasizes achievable performance per area and power. Software controls most aspects of data movement and instruction flow to improve memory system performance and core performance density. The design minimizes instruction latency while providing for fine grain clock control to reduce power.
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